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Level 1 trigger sorter implemented in hardware Grzegorz Kasprowicz 1 LHCb readout architecture Two levels of high-rate triggers L0 TRIGGER ST OT RICH ECAL HCAL MUON L0 FE L0 FE L0 FE L0 FE L0 FE L0 FE L0 FE L1 FE L1 FE L1 FE L1 FE L1 FE L1 FE L1 FE 40 MHz 1 MHz LHC CLK VELO 40 KHz TFC SYSTEM SWITCH SWITCH SORTER SWITCH Detector Front-End electronics Event building SWITCH READOUT NETWORK SFC SFC SFC SFC SFC SFC SWITCH SWITCH SWITCH SWITCH SWITCH SWITCH C C C C C C C C P P P P P P P P UUUU UUUU C C C C P P P P UUUU Grzegorz Kasprowicz C C C C P P P P UUUU C C C C P P P P UUUU C C C C P P P P UUUU CPU farm 2 Overview of the Timing and Fast Control (TFC) architecture L0 L1 Clock receiver and fanout LHC clock Trigger splitter Trigger splitter L1 Readout Supervisor Readout Supervisor L0 Throttle switch TTCtx Readout Supervisor L1 Throttle switch TFC switch TTCtx TTCtx TTCoc TTCoc TTCoc TTCoc TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx TTCrx VELO VELO L1 L1FE FE TTCtx TTC system ECAL VELO VELO VELO L0 FE L0 FE L0 L0FE FE Throttle OR VELO VELO VELO VELO L0 FE L0 FE L0 L0FE FE TTCtx ECAL VELO L1 L1FE FE Grzegorz Kasprowicz Throttle OR L0 Local trigger (optional) 3 Function blocs and data flow of Readout Supervisor I²C BOARD_INFO PROM CCPC PCI GLUE JTAG JTAG GPIO JTAG HUB PLD I²C MEZZANINE LBUS MEZZANINE L0 DATA L0_TRIGGER BUNCH_CURRENT Q_L0 Q_L0FE L0 TRIGGER L0 LINK L0 DATA L1 LINK L1 DATA FPGA FPGA L1 DBUF RAM L0_DATA GBE GbE RX L0 ABUF L1_TRIGGER RAM Q_L1 L1_TRG MEZZANINE LHC TTC(BST) L1 DATA L0_DATA FPGA TTCrx TTC_DATA GPS Q_MP L1BROADCAST & COMMANDS FPGA MEZZANINE TTCrs TTC MEZZANINE Q_L1 – trigger sorter block L1 DBUF - Data Buffer (SRAM) L0 ABUF - Accept Data Buffer (dual port SRAM) GbE RX – PM3386 chip based Gigabit Ethernet mezzanine board L1 LINK – TLK2501 – 1.6 GBPS transceiver Grzegorz Kasprowicz 4 Common L1 FE board DETECTOR STATUS L1 Trigger Sorter Tasks: Generation of control signals and receiving data from Ethernet mezzanine board Sorting triggers according to event id number Generation of control signals and data for TLK2501 transceiver Error detection – missing trigger, wrong event number range, timeout Counting processed triggers Generating long and short trigger broadcasts for Q_MP Generating addresses and signals for Accept Trigger Buffer (L0) and L1 Data Buffer Grzegorz Kasprowicz 5 To Front End Board How does it work? What is FPGA? L1 Data Buffer (RAM) BCLK RFCLK L1 TRG GBE From Readout Network D A T A D A T A control control PLL Ethernet DATA 6x32bit FIFO Mezzanine Board A D D R 1.6 GBPS transmitter (L1 Link) L1DBUF memory interface L1 Link interface TIMER control FPGA Event number comparator DATA L0 Ev Id Accept TRG Buffer (DPRAM) ADDR control Accept TRG memory Interface RX State machine Grzegorz Kasprowicz Error Detection Control interface LBUS To RS TX state machine 6 Detailed description A RX state machine reads the L1 trigger decision packets from the GbE RX via a 32-bit 80 MHz bus. The state machine drops the ten 32bit words of IP protocol and writes via FIFO the eight 32-bit words of L1 trigger data into the L1 DBUF using the Event ID as the address. A TX state machine compares the L0 Event ID of the incoming L1 triggers with the L0 Event ID of the next trigger to broadcast stored in the L0 Accept Buffer. Upon receiving the next L1 trigger to broadcast, the state machine prepares the broadcast frame, transmits it together with a broadcast request to the TTC broadcaster in the Q_MP module. The state machine also ensures that the L1 trigger accept broadcasts are spaced by a minimum of 20 ms and that the first L1 trigger reject broadcast after a L1 accept is transmitted after 900ns and otherwise at intervals of 400 ns, that’s why it needs timer block. Grzegorz Kasprowicz 7 How did I do this? Sample VHDL code Grzegorz Kasprowicz 8 Simulations Grzegorz Kasprowicz 9 Summary Speed: 4 milion events per second (much more than we need) Economy: much cheaper takes much less place consumes much less power than previously implemented Network Processor based sorter. Grzegorz Kasprowicz 10
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