Download Developing Sensor Network SoC Equipped with Low Power and

Baeg, Sanghyeon
Reliable & high Speed Computing Lab.
Hanyang University
Objectives
• Implementation of Reliable and
Low Power Sensor Node SoC
Contents
• Sensor Network of Nodes
• Why Low Power and Reliability
• Researches Undergoing
Main components of sensor nodes
• Microcontroller
• Transceiver
• External memory
• Power source
• One or more sensors
External Memory
Communication
device
Micro Controller
Power Source
Sensors

Energy is typically more limited in sensor
networks than in other wireless networks
because of the nature of the sensing devices and
the difficulty in recharging their power sources.
 Power
consumption in the sensor node is for
the Sensing, Communication and Data
Processing.

Ex) monitoring or at detecting phenomena.
Examples include office building environment
control, wild-life habitat monitoring, etc.
 More
energy is typically required for data co
mmunication in sensor node. Energy expenditure
is less for sensing and data processing.

The energy cost of transmitting 1 Kb a distance
of 100 m is approximately the same as that for
the executing 3 million instructions by 100 million
instructions per second/W processor
LOW POWER!!
 IC
should perform in accordance with
expectations for a predetermined period.
 Sudden death of sensor nodes cost replacing
and management efforts.
 Sensor nodes are typically exposed to
extreme environmental situations such as
temperature changes, weathers, animals.
 Mission
critical sensor nodes needs high prob
ability of surviving through self-guarding/
diagnosis features.
RELIABILITY!!
 Power
reduction for memories used in sensor
network
 Research
for cross talks in memory cells
Increasing memory density and
decreasing technology geometry
 Increasing capacitive cross talks
Reduced reliability because of
additional power consumption and
noise paths
 Becomes the source of
intermittent failure
Crosstalk in marginal size is not
detected by normal test
 Increasing costs for test
Test method using negative voltage
stress
 Testable method with low cost
 Analysis
for High-speed Interface Issues
 Chip
Schematic & Test Result

Micro Processor(8051) as underlying uP

Implement Processor in FPGA as initial stage with reduced
instruction for power saving
FPGA
MC8051_ALU
SIU
SIU
TMRCTR
TMRCTR
CONTROL
RAM
(128X8)
ROM
(64KX8)
RAM
(64KX8)

Customized IP Design is beneficial in low power design by
reducing unnecessary capacitance in design.
 Equipment
for development and testing
Logic Analyzer
Function Generator
BER Tester
Oscilloscope
Power Supply
FPGA Board
for Development &
Testing
Chip Test
Board(Interconnection
Testing Board)
Memory Test Board
 In
the second year of sensor hardware nodes
 Focused on development in low power and
reliable sensor node system
 Currently focusing on IP development
 Will be moving to FPGA system development
 Eventually, single chip solution
Thanks