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Synchronization over
packet-switching networks:
theory and applications
Raffaele Noro
PhD exam
Lausanne, May 12th 2000
Institute for computer
Communications and
Applications (ICA)
Swiss Federal Institute
of Technology,
Lausanne (EPFL)
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
2
Synchronization over packet-switching networks
• Voice
• Digital TV
•…
Synchronous
application
Synchronous
application
• Voice
• Digital TV
•…
Application-specific
synchronization
Circuit-switching
network
Synchronous
 Time Division Multiplexing
 Periodic, fixed-size frames

Global, static synchronization
Synchronous
application
Synchronous
application
Packet-switching
network
Asynchronous
 Statistical Multiplexing
 Bursty traffic, variable delay

Point-2-point, dynamic synchronization
Requirement of point-to-point synchronization:
 Synchronize the terminal clocks (fast, efficiently)
even in the presence of (higher) transmission jitter
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
3
The problem of synchronization in
packet-switching networks - part I
Variable delay
[Dmin…Dmax]
Generation

Packet-switching
network
Constant delay
Playout
de-jittering
buffer
Network jitter



Removed through the de-jittering buffer
Controlled playout of data
Optimal size: B= (Dmax- Dmin)· C
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
4
The problem of synchronization in
packet-switching networks - part II
Variable delay
[Dmin…Dmax]
Generation

Packet-switching
network


Playout
de-jittering
buffer
The Network Time Protocol (NTP, [Mills ’92])
provides only poor clock synchronization
guarantees (millisecond accuracy at best)
Physically dispersed clocks

Constant delay
Clock drift Df /f : speed of writing  speed of reading (on average)
Overflow (or underflow) of the de-jittering buffer
Time-to-overflow (or underflow) depends on buffer size, bitrate, and drift
B
T
C D f / f
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
Example: B= 10 kbits, C= 1 Mbps, Df/f= 10-4
(10 ms of jitter absorption in the buffer)
T= 100 seconds !!
 Introduction
 Theory
 Applications
 Conclusions
5
The problem of synchronization in
packet-switching networks
Variable delay
[Dmin…Dmax]
Generation

Packet-switching
network
Constant delay
Playout
de-jittering
buffer
Objective
Control and reduce to zero the clock drift within a convergence time
shorter than the time-to-overflow:
D f /f  0 within t < T
B
T
C D f / f
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
6
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
7
Synchronization of dispersed clocks
Packet-switching
network
Generation
Playout
Synch
algorithm
Clock of
transmitter
Clock of receiver
(free-running)
Timestamps
Timing of transm.
data
Timing of receiv.+ jitter
data
cTx(t)

2.

cRx(t)
Timestamping of data flow
1.
Synchonized
clock
cTx(t)
Timing of transm.
(original)
Information about the timing of data
Information about the transmitter clock
Processing of timestamps


Jitter limits the ability of the algorithm to reduce Df /f to zero
A convergence time is needed (… still not exceeding T )
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
8
State of the art: Phase-Locked Loops (PLLs)
PLL synchronization algorithm
Jitter
Reference clock
signal
PLL
Control
signal
Phase
comparator
xi
+
-

Periodic
pulses
VCO
(pulse
generator)
Synchronized clock
signal
Pulse
counter
cRxPLL(t)
Linear filtering of network jitter




Error
signal
Loop
filter
Local clock
Proportional-Integrative (PI) loop filter
Controlled frequency of the local oscillator (VCO)
Feedback used to trigger an error signal
Characteristics of linear filtering


For better accuracy  narrower bandwidth
With narrower bandwidth  longer response time
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
9
State of the art: Phase-Locked Loops (PLLs)
PLL synchronization algorithm
Jitter
Reference clock
signal
PLL
Phase
comparator
xi
+
-
Error
signal
Relative frequency drift, Kp= 0.0015, Ki= 0.000005
Control
signal
Loop
filter

Frequency drift (%)
0.02
Local clock
Periodic
pulses
VCO
(pulse
generator)
Network
jitter

Pulse
counter
network
residual
jitter
jitter
 20
Performance budget
Residual jitter
0
cRxPLL(t)
Accuracy
d0 
0.01
Synchronized clock
signal

d0
transient
time
 0.005
-0.01
Convergence time
-0.02
2000
4000
6000
8000
10000
The performance budget of PLLs (here: 0.005)
results below the expected performance budget
for packet-switching (ex: 0.2)
Time (s)
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
10
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
11
Least-square Linear Regression (LLR):
statistical filtering of network jitter
Clock model: cTx(t)= a cRx(t)+ b
[Mills, ’93; Cristian ‘89]
y(t)= CTx(t)
xN, yN
Estimation of (a, b) with the
N last collected (x, y)
N y i2   y i 
2
aLLR 
x1, y1
x(t)= CRx(t)
bLLR
N x i y i   x i  y i
y x y x y

N x y   x  y
i
i
i
Each cycle is triggered by the
reception of one timestamp
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
i
i
i
i
2
i
i
Recovered clock:
cTxLLR(t)= aLLR cRx(t)+ bLLR
 Introduction
 Theory
 Applications
 Conclusions
12
LLR circuitry and performance budget
yi
Mem.
^2
x
Mem.
Mem.
Mem.
-
+
+
+
+
Syi
Slope computation
^2
Syi2
Sxiyi
Sxi
-
+
xN
x(1- a)
âLLR
+
xa
xN
x

Low-pass filter
aLLR
-
+
+
-
xi
+
cTxLLR(t)
x
Timekeeping
cRx(t)
Relative frequency drift, N= 1000, a= 0.98
0.02


Residual jitter
0
-0.01
-0.02
Performance budget
  0.2
Convergence
time
Frequency drift (%)
d0  20
Network
jitter
0.01
Accuracy
2000
4000
6000
8000
10000
Time (s)
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
The performance budget of LLR (here: 0.2) is
1. Better than for PLLs (10 to 100 times)
2. Supports the needs of packet-switching
applications
 Introduction
 Theory
 Applications
 Conclusions
13
Comparative perfomance of LLR and PLL
0%
90%
99%
99.9%
Accuracy
(jitter resilience capability)
10
100
1000
10000
Region of interest for
packet-switching networks
LLR: Accuracy/ Conv.time  0.25 / t
(t= 0.1 s for this example)
PLL: Accuracy/ Conv.time  0.05
(nearly independent of t)
Convergence time (s)


Choose the parameters of LLR (N, a), and of PLL (Kp, Ki)
 trade-off between accuracy and rapidity
The trade-off is much better with the LLR
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
14
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
15
Applications and synchronization (I):
Circuit Emulation over IP networks
Objective

Support of circuit-switched leased-lines (e.g., T1) with high-speed IP
backbones (e.g., optical IP)
[ TDM-over-IP Forum, Geneva ‘99]
Relevance



Seamless migration to IP backbones without interruption of legacy
services
Transparent to the end-user
Can be simpler than VoIP solutions
Contributions



Definition of the functions
Design of the protocol
Performance assessment
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
16
Applications and synchronization (I):
Circuit Emulation over IP – definition of the functions

Emulation functions are allocated in a Circuit Emulation adapter
User
(e.g., T1/T3 leased lines)
TDM traffic
- Isochronous
- Periodic
Circuit Emulation
Adapter
• Jitter Removal
• Clock recovery
• Data structure
handling
IP Network
operator
IP
IP packets
backbone
- Asynchronous
- Aperiodic
IP
TDM
Circuit Emulation
LT
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
LT
Circuit Emulation
Adapter
IP
f
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
17
Applications and synchronization (I):
Circuit Emulation over IP – design of the protocol




Real-Time Protocol has been developed for real-time applications,
including VoIP applications [Schulzrinne, ’96]
Native features include timestamping and sequencing
Includes a control protocol – RTCP
Extended features can be added
Timestamping
& Sequencing
RTP
RTP-H
UDP
IP
UDP-H RTP-H
IP-H UDP-H RTP-H
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
Payload
Payload
Payload
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
18
Applications and synchronization (I):
Circuit Emulation over IP – design of the protocol
RTP packet
V PX
RTCP message
M
CC
PT
sequence number
timestamp
synchronization source (SSRC) id.
Other fields
Fixed
header
contributing source (CSRC) id. #1
d_max
x
structure
spacing
…
...
number
profile
SR extension
or
APP data
unused
length
source clock
Extension
header
indication (optional)

Payload of
Consecutive
Data Units

Payload


Data timing, jitter removal  timestamp
Clock recovery  source clock indication
Data handling  structure and spacing
Session information  RTCP messages
4 bytes
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
19
Applications and synchronization (I):
Circuit Emulation over IP – design of the adapter
Circuit Emulation adapter
Circuit Emulation adapter
non-idle
idle
Transmitter part
payload
RTP
packets
Receiver part
Packing
Leased
line
Structure
Spacing
Timestamps
+
Source clock
indications
Timestamp
Scheduling
Source clock
indications
Master
clock
Slave clock
(LLR/PLL)
RTP
packets
Scheduling
Leased
line
Structure
Spacing
Timestamp
Timestamp
Packing
payload
Receiver part
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
Transmitter part
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
20
Applications and synchronization (I):
Circuit Emulation over IP – performance assessment
End-to-end delay and loss rate for:



Best-effort service class
Expedited forwarding service class
Guaranteed service
Same nominal convergence time,
more stable end-to-end delay
with LLR (and more stable bitrate)
Network jitter model: [Bolot, ‘93]
End-to-end delay for a LLR with N= 1200 and a= 0.992
End-to-end delay for a PLL with Kp= 0.05 and Ki= .0005
220
220
200
200
Best Effort
180
160
Delay (ms)
180
Delay (ms)
Best Effort
Convergence time= 100 s
140
120
100
Exp. Forwarding
80
Guar. Service
160
Convergence time= 100 s
140
120
100
Exp. Forwarding
80
Guar. Service
60
60
0
50
100
150
Time (s)
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
0
50
100
150
Time (s)
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
21
Applications and synchronization (I):
Circuit Emulation over IP – performance assessment
Loss rate (log scale) for a LLR with N= 1200 and a= 0.992
Loss rate
10
10
10
10
0
0
10
-1
-1
Guar. Service
-2
10
Loss rate
10
Loss rate (log scale) for a PLL with Kp= 0.05 and Ki= .0005
Exp. Forwarding
-3
-2
10
Exp. Forwarding
-3
Best Effort
10
-4
0
Guar. Service
Best Effort
-4
50
100
150
10
0
50
Time (s)
100
150
Time (s)
Same nominal convergence time,
lower losses with LLR
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications — Application I: Circuit Emulation
 Conclusions
22
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
23
Applications and synchronization (II)
Synchronous AAL
Objective

Tranport of statistically multiplexed Variable Bitrate (VBR) traffic in ATM
networks with constant end-to-end delay
[AAL-1; AAL-2; AAL-3/4; AAL-5]
Relevance

Multimedia applications (Voice over ATM, video distribution)
Contributions


Design of the protocol
Performance assessment
Constant delay
Application
Synch AAL
ATM layer
Variable delay
ATM
switch
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
Application
Synch AAL
ATM layer
ATM
switch
 Introduction
 Theory
 Applications — Application II: Synchronous AAL
 Conclusions
24
Applications and synchronization (II)
Synchronous AAL – design of the protocol
Application layer
Synchronous AAL SDU
SSCS
4-byte timestamp added
by the synchronous AAL
(in units of microseconds)
TS
(AAL-5) CPCS SDU
Reserved CRC
Synchronous AAL
TS
CPCS (AAL-5)
(AAL-5) CPCS PDU
Padding Length
SAR (AAL-5)
ATM layer
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications — Application II: Synchronous AAL
 Conclusions
25
Applications and synchronization (II)
Synchronous AAL – design of the protocol
Synchronous AAL
(transmitter)
Synchronous AAL
(receiver)
AAL SDU
AAL SDU
Scheduling
Transmitter
clock
Timestamp
Self-synch
LLR/PLL Timestamp
SSCS
SSCS
AAL-5 CPCS SDU
AAL-5 CPCS trailer
CPCS
SAR
AAL SDU
AAL-5 CPCS SDU
AAL-5 CPCS trailer
CPCS
ATM cells payload
To the ATM network
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
SAR
ATM cells payload
From the ATM network
 Introduction
 Theory
 Applications — Application II: Synchronous AAL
 Conclusions
26
Applications and synchronization (II)
Synchronous AAL – performance assessment
Loss rate and rate discrepancy for:



376-byte AAL SDU
1 Mbps average rate
Erlang jitter distribution
Network jitter model:[Parekh, ’93; Singh, ’94; …]
10
Loss rate (log scale) for a LLR with
N= 10000 and a= 0.9992
-1
10
Loss rate (log scale) for a PLL with
Kp= 0.05 and Ki= 0.00025
-1
Convergence time= 100 s
Convergence time= 100 s
-2
10
10
-2
Loss rate
10
Loss rate
10
Same nominal convergence time,
lower loss with LLR during the
convergence time
-3
10
-4
0
50
100
150
200
250
10
-3
-4
0
50
100
Time (s)
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
150
200
250
Time (s)
 Introduction
 Theory
 Applications — Application II: Synchronous AAL
 Conclusions
27
Applications and synchronization (II)
Synchronous AAL – performance assessment
20
20
15
15
10
5
Difference of rate (kbps)
Difference of rate (kbps)
Difference between output and input rate
per each second of the session (LLR)
Average rate= 1 Mbps
Convergence time= 100 s
0
-5
0
-5
-15
-15
100
150
200
Time (s)
250
Convergence time= 100 s
5
-10
50
Average rate= 1 Mbps
10
-10
-20
0
Difference between output and input rate
per each second of the session (PLL)
-20
0
50
100
150
200
250
Time (s)
Same nominal convergence time,
more stable rate with LLR during
the convergence time
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications — Application II: Synchronous AAL
 Conclusions
28
Outline

Synchronization over packet-switching networks:
 Needs and problems in packet-switching networks

Theory:
 Conventional solution: Phase-Locked Loops (PLLs)
Do not scale to packet-switching networks

Proposed solution: Least-square Linear Regression (LLR)
Satisfies the new requirements

Applications:
 Circuit Emulation over IP Networks
 Synchronous ATM Adaptation Layer (AAL)
 Digital TV over packet-switching networks

Conclusions
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
29
Applications and synchronization (III)
Digital TV services
Objective

Synchronization of MPEG-2 systems over IP and ATM channels
[MPEG-2, ’94; Tryfonas ’99; …]
Relevance


Penetration of Digital TV services
Network-independence of MPEG codecs
Contribution

Performance assessment
Stored material
(films)
Live material
(TV)
Residential
user
Return
channel
Video
server
DVB: Video broadcast (cable, terrestrial and sat)
VoD: Video-on-demand (interactive TV)
 PPV: Pay-per-view (pre-scheduled TV programs)


Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
Distribution
network
The electron beam of TV
must be in-sync with the
video camera
Receiver/
decoder #1
DVD
Receiver/
decoder #N
 Introduction
 Theory
 Applications — Application III: Digital TV services
 Conclusions
The decoder must
synchronize to the server:
- generation of TV signal
- audio and video sync
30
Applications and synchronization (III)
Digital TV services– standardized protocol
Timestamping for:
 Intra- and inter-flow synchronization (DTS or PTS)
 Clock recovery and synchronization (PCR)
Audio
Audio and video part contain
Presentation TS referred to a
common timebase
Video
Compression
PES
packetizer
PTS/DTS
Video
PTS/DTS
Program
clock
Audio
Decompression
PES
depacketizer
Program
clock
PCR
Synch
LLR/PLL
Mux
Demux
Transmitter
Receiver
Transport
network
PCR
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
PCR
 Introduction
 Theory
 Applications — Application III: Digital TV services
 Conclusions
The PC Reference
is used to reconstruct
the common timebase
31
Applications and synchronization (III)
Digital TV services – performance assessment
Frequency reconstruction error of the System Clock



50 ms of network jitter
PCRs inserted each 100 ms
20 parts-per-million (tolerance dictated by MPEG-2)
Network jitter model: [Andreotti, ’95; Noro, ’99; …]
Frequency error (log scale) of the recovered clock
with N=4000 and a=0.99
Frequency error (log scale) of the recovered clock
with Kp= 0.002, Ki= 0.000001
1000
Frequency deviation (parts-per-million)
Frequency deviation (parts-per-million)
1000
Convergence time= 70 s
100
10
1
0.1
0.01
1000
2000
3000
Time (s)
4000
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
5000
Same nominal accuracy,
faster convergence with LLR
100
Convergence time= 2000 s
10
1
0.1
0.01
1000
2000
3000
Time (s)
 Introduction
 Theory
 Applications — Application III: Digital TV services
 Conclusions
4000
5000
32
Conclusions
Addressed problem

How to synchronize fast and efficiently dispersed clocks in the presence
of network jitter – satisfy new needs of packet-switching
Contributions

A solution based on LLR – overcomes limitations of conventional PLLs

Circuit Emulation over IP – support to legacy TDM leased-lines
Synchronous AAL – transport of ATM traffic with constant delay
Digital TV over packet-switching – distribution of MPEG-2 streams


Future work



Standardization of Circuit Emulation in the Internet community (RFCs)
Synchronization for mobile services
Global synchronization for IP networks
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
 Introduction
 Theory
 Applications
 Conclusions
33
Most relevant publications
Patents
1. ''Real-time remote inspection of high resolution images'', European Patent
n.EP946919A1, Issued Oct. 1999
2. R. Noro, J.P. Hubaux and M. Hamdi, ``Clock Synchronization over Data
Transmission Networks'', US Patent Application, filed July 1998, in progress
3. M. Hamdi, R. Noro and J.P. Hubaux, ``Fresh Packet First Scheduling for
Voice Traffic in Congested Networks'', US Patent Application, filed July
1998, in progress
Articles
1. ''Circuit Emulation over IP Networks'', Proc. of the IFIP 6th International
Workshop on Protocols for High-Speed Networks, Salem- MA, USA, Aug.
1999
2.
''Clock Synchronization of MPEG-2 Services over Packet Networks'',
Telecommunication Systems Journal, Baltzer Science Publisher, Vol. 11,
Nos. 1- 2, Mar. 1999,
3. ''Improving Clock Synchronization for MPEG-2 Services over ATM
Networks'', Proc. of the 4th Int. Workshop on Interactive Distributed
Multimedia Systems, Darmstadt, Germany, Sep. 1997, pp. 176- 188
Seminars
1. Design of a Circuit Emulation Protocol based on extended functionalities of
RTP, at the TDM over IP Forum, Geneva, Switzerland, Oct. 1999
2. Synchronization of Networks and Applications: a Survey, EPFL-SSC
Seminars Series, Lausanne, Switzerland, July 1999
Synchronization over packet-switching networks:
theory and applications
Raffaele Noro, PhD exam, May 12th 2000
34