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MULTIPLE CHOICE QUESTIONS
NA - NT
I.P. =
× 100
NA
Rule 1 Minimize overall part count
Step (C)
Rate the product on the worksheet:
If
I.P.  10%, then current design is outstanding
If
10% < I.P.  20%, then current design is very good
If
20% < I.P.  40%, then current design is good
If
40% < I.P.  60%, then current design is fair
If
I.P. > 60%, then current design is poor
Overall Assembly
1.
Minimize overall part count
2.
Minimize the use of separate fasteners
3.
Try fixturing features on base-part
4.
Minimize repositioning during assembly
5.
Optimize assembly sequence efficiency
Part Retrieval
6.
Make component easy to retrieve
7.
Design parts designed for selected type of assembly
Part Handling
8.
Design parts with end-to-end symmetry
9.
Design parts with symmetry about the axis of insertion
10.
Design non-symmetric parts clearly asymmetric
Part Mating
11.
Design for straight-line motions of assembly
12.
Design chamfers and features that facilitate insertion and self-alignment
13.
Design for the maximum part accessibility
PHA
1.
What is the subsystem or item under investigation?
2.
What is the mode of operation?
3.
What is the hazardous condition and why?
4.
What event(s) triggers the hazardous condition?
5.
What is the hazardous condition?
6.
What event(s) triggers the potential accident?
7.
What is the potential accident?
8.
What is the possible effect(s) of the accident?
9.
What is the classification of the severity of the hazard?
10. What measures are taken to contain or prevent occurences?
FAULT TREE ANALYSIS
The output fault occurrence probabilities for AND gate is:
FAND
m
  Fi
i 1
where
FAND
is the probability of occurrence of the AND gate output fault event
m
is the number of independent input fault events
Fi
is the probability of occurrence of input fault event i, for i=1, 2, …m
OUTPUT EVENT
FAND
Example:
F1 = 0.1
F2 = 0.05
AND
FAND = 0.1 * 0.05 = 0.005
INPUT EVENTS
F1
F2
FAULT TREE ANALYSIS
The output fault occurrence probabilities for OR gate:
FOR
m
 1   (1  Fi )
i 1
where
FOR is the probability of occurrence of the OR gate output fault event
m is the number of independent input fault events
Fi is the probability of occurrence of input fault event i, for i=1, 2, …m
FOR
OUTPUT EVENT
Example:
F1 = 0.1
OR
F2 = 0.05
INPUT EVENTS
F1
F2
FOR = 1 – (1 - 0.1)*(1- 0.05) = 0.145
Note: For small (i.e. less than 10 percent) occurrence probabilities of
input fault events of the OR gate, the above equation reduces to:
m
FOR   Fi
i 1
DIFFERENT TYPES OF FIT
Clearance fit
Limits of size defined such that a clearance always
results when mating parts are assembled
Interference fit
Limits of size are so prescribed that interference
always results when mating parts are assembled.
Transition fit
Limits of size are so prescribed that either clearance or an
interference may results when mating parts are assembled
Line fit
Limits of size are so prescribed that surface contact or
clearance may result when mating parts are assembled