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Instructions Addressing Modes
(Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design:
The Hardware/Software Interface, 3rd Ed., Morgan Kaufmann, 2007)
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COURSE CONTENTS
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Introduction
Instructions
Computer Arithmetic
Performance
Processor: Datapath
Processor: Control
Pipelining Techniques
Memory
Input/Output Devices
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Overview of MIPS
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Simple instructions all 32 bits wide
Very structured, no unnecessary baggage
Only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
funct
26 bit address
Addresses are not 32 bits
 How do we handle this with load and store instructions
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Addresses in
Branches and Jumps
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Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
j Label
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Next instruction is at Label if $t4≠$t5
Next instruction is at Label if $t4=$t5
Next instruction is at Label
Formats:
I
op
J
op
rs
rt
16 bit address
26 bit address
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Addresses in Branches
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Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
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Formats:
I
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Next instruction is at Label if $t4≠$t5
Next instruction is at Label if $t4=$t5
op
rs
rt
16 bit address
Could specify a register (like lw and sw) and add it to address
 Use Instruction Address Register (PC = program counter)
 Most branches are local (principle of locality)
Jump instructions just use high order bits of PC
 Address boundaries of 256 MB
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Addressing Modes
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Register addressing
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Base or displacement addressing
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operand is a constant within instruction
e.g. 3rd operand in addi $s1, $s2, 10
PC-relative addressing
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operand at memory location [register + constant (base)]
e.g. 2nd operand in lw $t0, 200($s1)
Immediate addressing
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operand is in a register, e.g. add $s1, $s2, $s3
address = PC (+4) + constant in instruction (*4)
e.g. 3rd operand in bne $s0, $s1, Exit
Pseudodirect addressing
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address = PC upper bits concatenated with 26-bit address in inst.
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Addressing Modes
1. Immediateaddressing
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Baseaddressing
op
rs
rt
Register
Memory
Address
+
Byte
Halfword
Word
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Addressing Modes
4. PC-relativeaddressing
op
rs
rt
PC
5. Pseudodirect addressing
op
Address
PC
Memory
Address
+
Word
Memory
Word
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Other Issues
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MIPS assembler accepts this pseudoinstruction even though it is not
found in MIPS architecture:
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move $t0, $t1 #$t0  $t1
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it translates it to: add $t0, $zero, $t1
Other pseudoinstructions: mult, blt, bge, etc.
Assembler keeps track of addresses of labels in symbol table
Details of assembler, linker, & loader are given in Appendix A
Details of MIPS instruction set & architecture in Appendix A
% frequency of instruction execution
Instruction Class
Arithmetic
gcc frequency
48%
spice frequency
50%
Data Transfer
33%
41%
Conditional branch
17%
8%
Jump & proc. call
2%
1%
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Instruction Set
Architecture Classes
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Use of accumulator (a default register):
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1 address instruction; e.g. add A: acc  acc + mem[A]
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e.g. EDSAC, IBM 701, DEC PDP-8, MC 6800, Intel 8008
Use of stack:
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0 address instruction;
e.g. add: top(stack)  top(stack) + next_top(stack)
Use of general purpose registers:
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2 address instruction; e.g. add A, B: A  A + B
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3 address instruction; e.g. add A,B,C: A  B + C
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load/store (reg/reg): e.g. MIPS, Sun’s SPARC, MC PowerPC, DEC Alpha
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memory/memory: e.g. DEC VAX
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memory/register: e.g. DEC VAX, IBM 360, DEC PDP-11, MC 68000,
Intel 80386
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RISC vs. CISC
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RISC -- Reduced Instruction Set Computer -- philosophy (instruction sets
measured by how well compilers used them)
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fixed instruction lengths
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load/store instruction sets
 all operands of ALU instructions are in registers
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limited addressing modes
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limited operations
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e.g. MIPS, Sun SPARC, HP PA-RISC, PowerPC (AIM), ARM, Renesas Tech.
SuperH (by Hitachi), ARM/Thumb, etc.
CISC – Complex Instruction Set Computer -- Implies
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fewer instructions in the set
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larger register file
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longer programs
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good for pipelining
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simpler control
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Chapter Summary
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Instruction Type
Instruction Format
RISC Design Principles
Assembly vs. Machine Language
Addressing Modes
Classes of Instruction Set Architecture
RISC vs. CISC
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