Download Arithmetic

COMPUTER ORGANISATION
Sri.S.A.Hariprasad
Sr.Lecturer
R.V.C.E Bangalore
SUMMARY OF THE TABLE
SIGN & MAGNITUE SYSTEM:
Negative value is
obtained by changing the sign bit (MSB)
SIGNED 1’S COMPLEMENT:
Negative number is
obtained by complementing each bit of the corresponding positive
number i.e (2n-1) –N
SIGNED 2’S COMPLEMENT:
Negative number is
obtained by taking 2’s complement of positive number
2 n-N
Range: - (2n-1) to + (2n-1-1)
ADDITION AND SUBSTRACTION
OF SIGNED NUMBERS
In unsigned operation if there is a carry from MSB position it is
called carry
In signed operations if there is a carry form MSB position it is called
end – around – carry
For signed arithmetic operations 2’s complement format is used
For signed arithmetic operation sign and magnitude and 1’s
complement format is not suitable
Rules for addition and subtraction of n – bit signed numbers
using 2’s complement representation
Addition of two n bit numbers:
Add n bits including sign bit and ignore carry – out from MSB
position. Sum will be correct till the answer are within range
Subtraction of two n bit numbers:
Eg: X-Y
Take 2’s complement for Y and add to X
X
Y
minuend
Subtrahend
 Result will be correct if the answers are within range
Neglect end – a round - carry
 If the results are out of range it is called arithmetic overflow
ARITHMETIC OVER FLOW
 Overflow will not occur when two numbers having opposite signs
added
Overflow can occur if two numbers having same signs are added
Overflow can be detected if
Cn
 Cn-1
=1
It can also be detected by using equation
Over flow = xn-1 yn-1sn-1 + xn yn-1 sn-1
MEMORY ADDRESSING
 BYTE ADDRESSABILITY
MEMORY ASSIGNMENT
LITTLE ENDIAN
BIG ENDIAN
n bit
LASTWORD
 In theoretical approach each row is called as WORD or LOCATION
But in practice each location contains one byte information, which is
referred as byte addressability
BIG ENDIAN AND LITTLE ENDIAN
If the least significant byte of the word occupies the lower address
in memory it is called Little endian scheme
Eg: INTEL 8085 INTEL 8086 Processor uses this scheme
 If the most significant byte of the word occupies the lower address in
memory it is called Big endian scheme
Eg: Motorola and Power PC Processors
EXAMPLE TO LITTLE ENDIAN SCHEME
Eg: 46,78,96,54 (32 bit data)
H BYTE
L BYTE
8000
8001
8002
54
96
78
8003
46
BIG ENDIAN SCHEME
Eg: 46,78,96,54
H BYTE
8000
L BYTE
46
78
96
54
SUMMARY:
In case of 16 bit data, aligned words begin at byte addresses of
0,2,4,………………………….
In case of 32 bit data, aligned words begin at byte address of
0,4,8,………………………….
In case of 64 bit data, aligned words begin at byte addresses of
0,8,16,………………………..
In some cases words can start at an arbitrary byte address also then,
we say that word locations are unaligned
MEMORY OPERATION
LOAD (READ OR FETCH)
STORE (WRITE)
READ OR FETCH
Processor sends addresses selects the particular
memory location
Issues read signal
Reads the data via data bus (memory sends data to
the processor)
STORE OR WRITE
Processor sends address and selects the particular
memory location
Issues write signal
Sends the data via data bus and write into the selected
particular memory location
INSTRUCTIONS AND
INSTRUCTION SEQUENCING
INSTRUCTION
PROGRAM
INSTRUCTION SET ARCHITECTURE
BASIC FOUR TYPES OF OPERATION
REGISTER TRANSFER NOTATION
ASSEMBLY LANGUAGE NOTATION
TYPES OF INSTRUCTION
INSTRUCTION
SEQUENCING
EXECUTION
BRANCHING
CONDITION CODES
AND
STRIAGHT
LINE
INSTRUCTION SET ARCHITECTURE:-Complete
instruction set of the processor
BASIC 4 TYPES OF OPERATION:Data transfer between memory and processor register
Arithmetic and logic operation
Program sequencing and control
I/O transfer
Register transfer notation (RTN)
 Memory locations, registers and I/O register names are identified
by a symbolic name in uppercase alphabets
 SUM, LOOK_UP, are memory location which
indicates the address of memory location
 R1, R2 are register names
DATA_IN, OUT_BUFFER are I/O register names
 Contents of location is indicated by using square brackets
RHS of RTN always denotes a values, and is called Source
LHS of RTN always denotes a symbolic name where value is to
be stored and is called destination
Source contents are not modified
Destination contents are overwritten
Examples of RTN statements
1. R2
[LOCN]
2. R4
[R3] +[R2]
ASSEMBLY LANGUAGE NOTATION
RTN is easy to understand and but cannot be used to represent
machine instructions
Mnemonics can be converted to machine language, which
processor understands using assembler
Eg:
1. MOVE LOCN, R2
2. ADD
R3, R2, R4
TYPE OF INSTRUCTION
 Three
address instruction
Syntax: Operation source 1, source 2, destination
Eg: ADD D,E,F
where D,E,F are memory location
Advantage: Single instruction can perform the complete operation
Disadvantage : Instruction code will be too large to fit in one
word location in memory
TWO ADDRESS INSTRUCTION
 Syntax : Operation source, destination
Eg:
MOVE E,F
ADD
D,F
MOVE D,F
OR
ADD
E,F
 Disadvantage: Single instruction is not sufficient to perform the
entire operation.
ONE ADDRESS INSTRUCTION
 Syntax- Operation source/destination
In this type either a source or destination operand is
mentioned in the instruction
Other operand is implied to be a processor register
called Accumulator
Eg: ADD B (general)
1. Load D;
ACC
[memlocation _D]
2. ADD E;
ACC
(ACC) +(E)
3. STORE F;
memlocation_ F
(ACC )
Load E
ACC
[Memlocation –E]
ADD D
ACC
(ACC) + (E)
STORE F
(memlocation F)
(A)
Zero address instruction
Location of all operands are defined implicitly
Operands are stored in a structure called pushdown stack
Note:
Basic load, store, add, operation
Load A,
Ri
Stores Ri , B
Add B, Ri
If processor supports ALU operations one data in memory and
other in register then the instruction sequence is
MOVE
ADD
D, Ri
E, Ri
MOVE Ri, F
If processor supports ALU operations only with registers then
one has to follow the instruction sequence given below
 LOAD
D, Ri
LOAD
E, Rj
ADD
Ri, Rj
MOVE
Rj, F
INSTRUCTION EXECUTION &
STRIAGHT LINGE SEQUENCING
(PC)
MOVE D, R1
i
i +4
ADD E, R1
i +8
MOVE R1, F
Instruction
D
Data
E
F
Program for F
[D] +[E]
PC – Program counter: hold the address of the next instruction to
be executed
Straight line sequencing: If fetching and executing of instructions
is carried out one by one from successive addresses of memory, it
is called straight line sequencing.
Major two phase of instruction execution
 Instruction fetch phase: Instruction is fetched form
memory and is placed in instruction register IR
Instruction execute phase: Contents of IR is decoded and
processor carries out the operation either by reading data
from memory or registers.
BRANCHING
Branch instruction are those which changes the normal sequence
of execution.
Sequence can be changed either conditionally or unconditionally.
Accordingly we have conditional branch instructions and
unconditional branch instruction.
Unconditional branch instruction changes the sequence only when
certain conditions are met.
Unconditional branch instruction changes the sequence of
execution irrespective of condition of the results.
CONDITION CODES
 CONDITIONAL CODE FLAGS:
 N – Negative 1 if results are Negative
0 if results are Positive
Z – Zero
1 if results are Zero
0 if results are Non zero
V – Overflow
1 if arithmetic overflow occurs
0 non overflow occurs
C – Carry
1 if carry and from MSB bit
0 if there is no carry from MSB bit