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Assembly Language for Intel-Based
Computers
Kip Irvine
Chapter 2: IA-32 Processor
Architecture
General Concepts
• Basic microcomputer design
• Instruction execution cycle
• Reading from memory
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
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Examples
2
Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of execution steps
• ALU performs arithmetic and bitwise processing
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
clock
control bus
address bus
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
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Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events
one cycle
1
0
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
4
Instruction Execution Cycle
PC
I-1
memory
op1
op2
fetch
read
registers
registers
write
I-1
write
Fetch
Decode
Fetch operands
Execute
Store output
instruction
register
decode
•
•
•
•
•
program
I-2 I-3 I-4
flags
ALU
execute
(output)
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
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Examples
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Multi-Stage Pipeline
• Instruction execution divided into discrete stages
Stages
S1
1
S2
S5
I-1
4
I-1
5
I-1
6
7
8
9
I-1
I-2
I-2
I-2
10
I-2
11
I-2
12
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
S6
I-1
3
Cycles
S4
I-1
2
Example of a nonpipelined processor.
Many wasted cycles.
S3
I-2
Web site
Examples
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Pipelined Execution
• More efficient use of cycles, greater throughput of instructions:
Stages
Cycles
S1
1
I-1
2
I-2
3
4
5
S2
S3
S4
S5
S6
For k states and n
instructions, the
number of required
cycles is:
I-1
I-2
I-1
I-2
I-1
I-2
6
7
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
I-1
I-2
I-1
k + (n – 1)
I-2
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Examples
7
Reading from Memory
•
Multiple machine cycles are required when reading from memory,
because it responds much more slowly than the CPU. The steps are:
• address placed on address bus
• Read Line (RD) set low
• CPU waits one cycle for memory to respond
• Read Line (RD) goes to 1, indicating that the data is on the data
bus
Cycle 1
Cycle 2
Cycle 3
Cycle 4
CLK
Address
ADDR
RD
Data
DATA
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
8
Basic Execution Environment
•
•
•
•
•
•
Addressable memory
General-purpose registers
Index and base registers
Specialized register uses
Status flags
Floating-point
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
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General-Purpose Registers
Named storage locations inside the CPU, optimized for
speed.
32-bit General-Purpose Registers
EAX
EBP
EBX
ESP
ECX
ESI
EDX
EDI
16-bit Segment Registers
EFLAGS
EIP
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
CS
ES
SS
FS
DS
GS
Web site
Examples
10
Accessing Parts of Registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8
8
AH
AL
AX
EAX
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
8 bits + 8 bits
16 bits
32 bits
Web site
Examples
11
Index and Base Registers
• Some registers have only a 16-bit name for their
lower half:
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
12
Some Specialized Register Uses (1 of 2)
• General-Purpose
•
•
•
•
•
EAX – accumulator
ECX – loop counter
ESP – stack pointer
ESI, EDI – index registers
EBP – extended frame pointer
• Segment
•
•
•
•
CS – code segment
DS – data segment
SS – stack segment
ES, FS, GS - additional segments
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
13
Some Specialized Register Uses (2 of 2)
• EIP – instruction pointer
• EFLAGS
• status and control flags
• each flag is a single binary bit
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
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Examples
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Status Flags
• Carry
• unsigned arithmetic out of range
• Overflow
• signed arithmetic out of range
• Sign
• result is negative
• Zero
• result is zero
• Auxiliary Carry
• carry from bit 3 to bit 4
• Parity
• sum of 1 bits is an even number
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
15
Carry and Overflow
• Carry is important when …
• Adding or subtracting unsigned integers
• Indicates that the unsigned sum is out of range
• Overflow is important when …
• Adding or subtracting signed integers
• Indicates that the signed sum is out of range
• Overflow occurs when
• Adding two positive numbers and the sum is negative
• Adding two negative numbers and the sum is positive
• Can happen because of the fixed number of sum bits
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
16
Carry and Overflow Examples
• We can have carry without overflow and vice-versa
• Four cases are possible
1
0
0
0
0
1
1
1
1
1
15
+
1
1
1
1
0
0
0
0
1
1
1
1
15
+
0
0
0
0
1
0
0
0
8
1
1
1
1
0
1
0
1 245 (-11)
0
0
0
1
0
1
1
1
23
0
0
0
0
0
11
0
0
Carry = 0
Overflow = 0
Carry = 1
1
1
0
1
0
0
1
1
1
1
79
+
4
Overflow = 0
1
1
1
1
0
1
1
0
1
0 218 (-38)
+
0
1
0
0
0
0
0
0
64
1
0
0
1
1
1
0
1 157 (-99)
1
0
0
0
1
1
1
1
143
(-113)
0
1
1
1
0
1
1
1
Carry = 0
Overflow = 1
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Carry = 1
Web site
119
Overflow = 1
Examples
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Addressable Memory
• Protected mode
• 4 GB
• 32-bit address
• Real-address and Virtual-8086 modes
• 1 MB space
• 20-bit address
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
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Examples
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Real-Address mode
• 1 MB RAM maximum addressable
• Application programs can access any area
of memory
• Single tasking
• Supported by MS-DOS operating system
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
19
Segmented Memory
Segmented memory addressing: absolute (linear) address is a
combination of a 16-bit segment value added to a 16-bit offset
F0000
E0000
8000:FFFF
D0000
C0000
B0000
A0000
one segment
90000
80000
70000
60000
8000:0250
50000
0250
40000
30000
8000:0000
20000
10000
seg
00000
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
ofs
Web site
Examples
20
Calculating Linear Addresses
• Given a segment address, multiply it by 16 (add a
hexadecimal zero), and add it to the offset
• Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset:
0 1 0 0
Linear address:
0 9 0 1 0
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
21
Calculating Linear Addresses
What linear address corresponds to the segment/offset
address 028F:0030?
028F0 + 0030 = 02920
Always use hexadecimal notation for addresses.
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
22
Calculating Linear Addresses
What segment addresses correspond to the linear address
28F30h?
Many different segment-offset addresses can produce the
linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
Web site
Examples
23
Intel Registers
32-bit General-Purpose Registers
EAX
EBP
EBX
ESP
ECX
ESI
EDX
EDI
16-bit Segment Registers
EFLAGS
EIP
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.
CS
ES
SS
FS
DS
GS
Web site
Examples
24