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2010 R&E Computer System Education & Research
Lecture 8. MIPS Instructions #1 – Arithmetic and
Logical Instructions
Prof. Taeweon Suh
Computer Science Education
Korea University
MIPS
• Stanford University led by John Hennessy
started work on MIPS in 1981
 John is currently a president of Stanford Univ.
• MIPS has 32-bit and 64-bit versions
 We focus on 32-bit version
• Currently, MIPS is primarily used in many
embedded systems
 Nintendo 64
 Sony Playstation and Playstation 2
 Cisco routers
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CISC vs RISC
• CISC (Complex Instruction Set Computer)
 One assembly instruction does many (complex) job
 Variable length instruction
 Example: x86 (Intel, AMD)
• RISC (Reduced Instruction Set Computer)




Each assembly instruction does a small (unit) job
Fixed-length instruction
Load/Store Architecture
Example: MIPS, ARM
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• Let’s go over MIPS instructions
 Again, if you completely understand one CPU, it is
pretty easy to understand other CPUs
• For the term project, you should implement the
MIPS ISA into hardware
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Overview of a MIPS Operation
(Computer Hardware)
• Every computer must be able to perform arithmetic
• MIPS arithmetic in assembly form
add
R3, R1, R5
# R3 = R1 + R5
• An instruction operates on operands (R3, R1, and R5 are all operands)
• # indicate a comment, so assembler ignores it
 Operands of arithmetic instructions come from special locations called
registers or from the immediate field in instructions
• All CPUs (x86, PowerPC, MIPS…) have registers inside
 Registers are visible to the programmers
• Again, abstraction layer!
• When CPU completes a arithmetic operation (such as addition), its result is stored in a
register
 MIPS has a register file consisting of 32 32-bit registers
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Simple Illustration of the CPU Internal
Organization
add
Registers
R3, R1, R5
# R3 = R1 + R5
CPU (MIPS)
32 bits
R0
R1
R2
R1
Memory
Address Bus
R3
…
+
R3
add R3, R1, R5
R5
Data Bus
R30
R31
• What kinds of other instructions do you think CPU should have?
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MIPS Register File
• MIPS register file has thirty-two 32bit registers
Register File
 Two read ports
 One write port
32 bits
src1 addr
• Registers are implemented with
flip-flops
src2 addr
5
R0
32 src1
5
R1
R2
data
R3
 For example, one 32-bit register
requires 32 flop-flops
dst addr
• Registers are much faster than
main memory since they reside
inside CPU
write data
5
…
32
R30
32 src2
data
R31
write control
• So, compilers strive to use registers
when translating high-level code to
assembly code
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Register File in Verilog
module regfile(input
clk,
input
we,
input [4:0] ra1, ra2, wa,
input [31:0] wd,
output [31:0] rd1, rd2);
Register File
32 bits
ra1[4:0]
reg [31:0] rf[31:0];
//
//
//
//
ra2[4:0]
three ported register file
read two ports combinationally
write third port on rising edge of clock
register 0 hardwired to 0
5
R0
5
R1
R2
32
rd1
32
rd2
R3
wa3
wd3
always @(posedge clk)
if (we) rf[wa] <= wd;
5
…
32
R30
R31
we3
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
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MIPS Register Convention
Name
$zero
$at
$v0 - $v1
$a0 - $a3
$t0 - $t7
$s0 - $s7
$t8 - $t9
$gp
$sp
$fp
$ra
Register
Number
0
Usage
constant 0 (hardwired)
Preserve
on call?
n.a.
1
2-3
4-7
8-15
16-23
24-25
28
29
30
31
reserved for assembler
returned values
arguments
temporaries
saved values
temporaries
global pointer
stack pointer
frame pointer
return address
n.a.
no
yes
no
yes
no
yes
yes
yes
yes
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MIPS-32 CPU
Registers
• Instruction categories
 Arithmetic and Logical
(Integer)
 Load/Store
 Jump and Branch
 Floating Point
R0 - R31
PC
HI
LO
3 Instruction Formats: all 32 bits wide
opcode
rs
rt
opcode
rs
rt
opcode
rd
sa
immediate
jump target
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funct
R format
I format
J format
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MIPS Instruction Fields
• MIPS fields are given names to make them
easier to refer to
32-bit
rs
op
rt
rd
shamt
funct
op
6-bits
opcode that specifies the operation
rs
5-bits
register of the first source operand
rt
5-bits
register of the second source operand
rd
5-bits
register of the result’s destination
shamt 5-bits
shift amount (for shift instructions)
funct
function code augmenting the opcode
6-bits
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MIPS (RISC) Design Principles
• Simplicity favors regularity
 Fixed size instructions
 Small number of instruction formats
 Opcode always occupies the first 6 bits in instructions
• Smaller is faster
 Limited instruction set
 Limited number of registers in register file
 Limited number of addressing modes
• Make the common case fast
 Arithmetic operands from the register file (load-store machine)
 Allow instructions to contain immediate operands
• Good design demands good compromises
 Three instruction formats
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MIPS Essential Instructions
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MIPS Instructions
• For the complete instruction set, refer to the
“Appendix B.10 MIPS R2000 Assembly Language”
• For detailed information on the MIPS instruction set,
refer to the Appendix A (page 469) in MIPS R4000
specification linked in the class web
• We are going to cover essential and important
instructions in this class
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MIPS Arithmetic Instructions
• MIPS Arithmetic instructions include add, sub,
addi, addiu, mult, div and some more
 Check out the appendix for the list of all arithmetic
instructions
High-level code
MIPS assembly code
compile
# $s0 = a, $s1 = b, $s2 = c
add $s0, $s1, $s2
a = b + c
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MIPS Arithmetic Instruction - add
• Instruction format (R format)
add
rd, rs, rt
• Example:
add
$t0, $s1, $s2 # $t0 <= $s1 + $s2
Name
opcode
0
rs
rt
17
18
rd
sa
8
0
funct
32
MIPS architect defines the opcode and function
binary
hexadecimal
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
000000
10001
10010 01000 00000
100000
$gp
28
000000
10001
10010 01000 00000
100000
$sp
29
$fp
30
$ra
31
0x0232 4020
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MIPS Arithmetic Instruction - sub
• Instruction format (R format)
sub
rd, rs, rt
• Example:
sub $t2, $s3, $s4 # $t2 <= $s3 - $s4
opcode
0
rs
rt
19
20
rd
sa
10
0
funct
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MIPS architect defines the opcode and function
binary
hexadecimal
Name
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
000000
10011
10100 01010 00000
100010
$gp
28
000000
10011
10100 01010 00000
100010
$sp
29
$fp
30
$ra
31
0x0274 5022
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Immediate
• R-type instructions have all 3 operands in registers
• Operands could be stored in instructions itself in Itype instructions
 They are called immediates because they are immediately
available from the instructions (I-type)
• They do not require a register or memory access
 16-bit immediate field in MIPS instructions limits values to
the range of (-215 ~ +215–1) since it uses 2’s complement
opcode
rs
rt
immediate
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I format
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Revisiting 2’s Complement Number
• In hardware design of computer arithmetic, the 2s
complement number provides a convenient and
simple way to do addition and subtraction of
unsigned and signed numbers
• Given an n-bit number N in binary, the 2s
complement of N is defined as
2n – N for N ≠ 0
0 for N = 0
 Example:
• In 4-bit number, 3 is 4’b0011
 2’s complement of 3: 24 -3 = 4’b1101
• A fast way to get a 2s complement number is to flip
all the bits and add “1”.
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Number System Comparison with N-bit
Number System
Range
Unsigned
[0, 2N-1]
Sign/Magnitude
[-(2N-1-1), 2N-1-1]
2’s Complement
[-2N-1, 2N-1-1]
• Thus, 16-bit can represent a range of
 Unsigned: [ 0 ~ +(216-1)] = [ 0 ~ +65535]
 Sign/Magnitute: [-(216-1-1) ~ +(216-1-1)] =[-32767 ~ +32867]
 2’s complement: [-216-1 ~ +216-1-1] =[-32768 ~ +32867]
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MIPS Arithmetic Instruction - addi
• Instruction format (I format)
addi
rt, rs, imm
• Example:
addi $t0, $s3, -12
#$t0 = $s3 + (-12)
Name
opcode
8
binary
hexadecimal
rs
rt
19
immediate
8
-12
001000
10011
01000 11111 11111
110100
001000
10011
01000 11111 11111
110100
0x2268 FFF4
21
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
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MIPS Logical Instructions
• MIPS logical operations include and, andi, or,
ori, xor, nor, sll, slr, sra and some
more
• Logical operations operate bit-by-bit on 2 source
operands and write the result to the destination
register
High-level code
MIPS assembly code
compile
# $s0 = a, $s1 = b, $s2 = c
and $s0, $s1, $s2
a = b & c
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AND, OR, and NOR Usages
• and, or, nor
– and: useful for masking bits
•
Example: mask all but the least significant byte of a value:
0xF234012F AND 0x000000FF = 0x0000002F
– or: useful for combining bit fields
•
–
Example: combine 0xF2340000 with 0x000012BC:
0xF2340000 OR 0x000012BC = 0xF23412BC
nor: useful for inverting bits:
•
Example: A NOR $0 = NOT A
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Logical Instruction Examples
Source Registers
$s1 1111 1111 1111 1111 0000 0000 0000 0000
$s2 0100 0110 1010 0001 1111 0000 1011 0111
Assembly Code
Result
and $s3, $s1, $s2
$s3
or
$s4, $s1, $s2
$s4
xor $s5, $s1, $s2
$s5
nor $s6, $s1, $s2
$s6
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Logical Instruction Examples
Source Registers
$s1 1111 1111 1111 1111 0000 0000 0000 0000
$s2 0100 0110 1010 0001 1111 0000 1011 0111
Assembly Code
Result
and $s3, $s1, $s2
$s3 0100 0110 1010 0001 0000 0000 0000 0000
or
$s4, $s1, $s2
$s4 1111 1111 1111 1111 1111 0000 1011 0111
xor $s5, $s1, $s2
$s5 1011 1001 0101 1110 1111 0000 1011 0111
nor $s6, $s1, $s2
$s6 0000 0000 0000 0000 0000 1111 0100 1000
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MIPS Logical Instructions
• Instruction format (R format)
and (or, nor)
rd, rs, rt
• Examples:
and $t0, $t1, $t2
#$t0 = $t1 & $t2
or
#$t0 = $t1 | $t2
$t0, $t1, $t2
nor $t0, $t1, $t2
opcode
0
binary
hexadecimal
Name
#$t0 = not($t1 | $t2)
rs
rt
9
10
rd
sa
8
0
funct
39
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
000000
01001
01010 01000 00000
100111
$sp
29
000000
01001
01010 01000 00000
100111
$fp
30
$ra
31
0x012A 4027
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MIPS Logical Instructions (Cont)
• Instruction format (I format)
andi(ori) rt, rs, imm
• Example:
andi $t0, $t1, 0xFF00
#$t0 = $t1 & ff00
ori
#$t0 = $t1 | ff00
opcode
13
binary
hexadecimal
$t0, $t1, 0xFF00
rs
rt
9
8
immediate
0xFF00
Name
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
001101
01001
01000 11111 11100
000000
$gp
28
001101
01001
01000 11111 11100
000000
$sp
29
$fp
30
$ra
31
0x3528 FF00
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Sign Extension & Zero Extension
• Most MIPS instructions sign-extend the immediate
 For example, addi does sign-extension to support
both positive and negative immediates
• An exception to the rule is that logical operations
(andi, ori, xori) place 0’s in the upper half
 This is called zero extension
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Revisiting Basic Shifting
• Shift directions
 Left (multiply by 2)
 Right (divide by 2)
• Take floor value if the result is not an integer
• Floor value of X (or X) is the greatest integer number less
than or equal to X, E.g.
 5/2 = 2
 -3/2 = -2
• Shift types
 Logical (or unsigned)
 Arithmetic (or signed)
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Revisiting Logical Shift
• Shift Left
 MSB: Shifted out
 LSB: Shifted in with a “0”
 Examples:
• (11001011 << 1) = 10010110
• (11001011 << 3) = 01011000
• Shift right
 MSB: Shifted in with a “0”
 LSB: Shifted out
 Examples:
• (11001011 >> 1) = 01100101
• (11001011 >> 3) = 00011001
• Logic shifts can be useful to perform multiplication or division of
unsigned integer
• Logical shift right takes floor value if the result is not integer
Modified from Prof H.H.Lee’s slide, Georgia Tech
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Revisiting Arithmetic Shift
• Shift left
 MSB: Shifted out, however, be aware of overflow/underflow
 LSB: Shifted in with a “0”
 Examples:
• (1100 <<< 1) = 1000
• (1100 <<< 3) = 0000 (Incorrect!)  Underflow
• Shift right
 MSB: Retain “sign bit”
 LSB: Shifted out
 Examples:
• (1100 >>> 1) = 1110 (Retain sign bit)
• (1100 >> >3) = 1111 (-4/8 = -1 )  Floor value of -0.5
• Arithmetic shifts can be useful to perform multiplication or
division of signed integer
• Arithmetic shift right takes floor value if the result is not integer
Modified from Prof H.H.Lee’s slide, Georgia Tech
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MIPS Shift Instructions
• Shift instructions shift the value in a register left or right by
up to 31 bits (5-bit shamt field)
 sll rd, rt, shamt: shift left logical
 srl rd, rt, shamt: shift right logical
 sra rd, rt, shamt: shift right arithmetic (sign-extension)
Name
• Instruction Format (R format)
• Examples:
sll $t0, $s1, 4
srl $t2, $s0, 8
sra $s3, $s1, 4
opcode
0
rs
0
#$t0 = $s1 << 4 bits
#$t2 = $s0 >> 8 bits
#$t0 = $s1 << 4 bits
rt
17
rd
sa
19
4
Binary ?
Hexadecimal: ?
32
funct
3
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
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MIPS Shift Instructions (Cont)
• MIPS also has variable-shift instructions
 sllv rd, rt, rs: shift left logical variable
 srlv rd, rt, rs: shift right logical variable
 srav rd, rt, rs: shift right arithmetic variable
• Instruction Format (R format)
• Examples:
sllv $s3, $s1, $s2
srlv $s4, $s1, $s2
srav $s5, $s1, $s2
opcode
0
rs
18
Name
#$s3 = $s1 << $s2
#$s4 = $s1 >> $s2
#$s5 = $s1 << $s2
rt
17
rd
sa
21
0
Binary ?
Hexadecimal: ?
33
funct
7
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
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