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www.bookspar.com | Website for students | VTU NOTES COMPUTER ORGANIZATION By: Chandrashekar M A,CSE, SSE Chapter 2: Machine Instructions and Programs www.bookspar.com | Website for students | VTU NOTES Memory Location and Addresses In memory of computer, there are Number and character operands Instructions Memory consists of Millions of storage cells, Each cell can hold a bit ( 0 or 1 ) of information So each bit can hold a very small amount of information Memory is organized so that a group of n bits can be stored or retrieved in a single, basic operation Each group of n bits is referred to as word n is called as wordlength www.bookspar.com | Website for students | VTU NOTES n bits first word second word • • • i th word • • • last word Memory words. www.bookspar.com | Website for students | VTU NOTES Contd… • Range of word length of modern computers • 16 to 64 bits • Group of 8 bits referred to a byte • If the word length is 32 bits • A single word can store a 32-bit 2’s complement number • Or • Four ASCII characters • As shown in the figure www.bookspar.com | Website for students | VTU NOTES 32 bits b1 • • • b31 b30 b0 Sign bit: b31= 0 for positive numbers b31= 1 for negative numbers (a) A signed integer 8 bits 8 bits 8 bits 8 bits ASCII character ASCII character ASCII character ASCII character (b) Four characters Examples of encoded information in a 32-bit word. www.bookspar.com | Website for students | VTU NOTES Addresses • Access to memory to store or retrieve a single item of info ( either a byte or a word ) requires distinct names or addresses for each item location • normally used addresses => 0 to 2k -1 as addresses of successive memory locations • The 2k addresses constitute address space of the computer • 24-bit address generates an address space of 224 locations = 16M locations • 32-bit ? www.bookspar.com | Website for students | VTU NOTES Byte Addressability • A byte is always 8-bit • Word length ranges from 16 to 64 bits. • Impractical to assign distinct addresses to individual bit • • • • locations Most practical? Byte-addressable memory Byte locations have addresses 0,1,2,.. If the word length of the machine is 32-bits, then successive words are located at addresses ? www.bookspar.com | Website for students | VTU NOTES Big-Endian and Little-Endian Assignments • 2 ways byte addresses can be assigned across words • Big-endian when • Lower byte addresses for more significant bytes (leftmost bytes ) of the word. • Little-endian when • Lower bytes addresses used for less significant bytes (right most bytes ) of the word. • In both cases 0,4,8 .. are taken as addresses of successive words in the memory www.bookspar.com | Website for students | VTU NOTES Word address Byte address Byte address 0 0 1 2 3 0 3 2 1 0 4 4 5 6 7 4 7 6 5 4 • • • k 2 -4 k 2 -4 k 2 -3 • • • k 2- 2 k 2 - 1 k 2 - 4 (a) Big-endian assignment Byte and word addressing. k 2- 1 k 2 - 2 k 2 -3 k 2 -4 (b) Little-endian assignment www.bookspar.com | Website for students | VTU NOTES Word Alignment • Words are said to be aligned in memory if they begin at a byte address that is a multiple of the number of bytes in a word • Eg : if wordlength is 16bits, aligned words begin at byte addresses 0,2,4,…. • If word length is 32 bits, aligned words begin at 0,4,8 etc… • If the words don’t begin at byte address that is a multiple of no of bytes in the word, then words are said to have unaligned addresses www.bookspar.com | Website for students | VTU NOTES Accessing numbers, characters and strings Number By its word address as it usually occupies one word Character By byte address Strings They are of variable length Beginning of the string by giving the beginning byte address which contains first character Successive bytes contains successive characters Termination? Either by a special control character Or a separate memory word location/ register containing a number indicating the string length www.bookspar.com | Website for students | VTU NOTES Problems Given that a memory has 32-bit address & is byteaddressable, what is the size of the memory(in bytes)? 2. Given that a memory has 24-bit address & is wordaddressable with a word length of 32 bits, what is the size of the memory(in bytes)? 3. Given that a memory has 16-bit address and is byte addressable. Word length is 32 bits. How many words can we store in such a memory? 1. www.bookspar.com | Website for students | VTU NOTES Answers 4GB 2. 64MB 3. 16K words 1. www.bookspar.com | Website for students | VTU NOTES Memory Operations • Both program instructions and data operands are stored in memory • To execute an instruction • Processor control circuits must cause the word(s) containing the instruction to be transferred from the memory to the processor • Operands and results must also be moved between memory and the processor • Two basic operations involving the memory • Load ( or Read or Fetch ) • Store ( or Write ) www.bookspar.com | Website for students | VTU NOTES Memory Operations – LOAD operation • Load transfers a copy of the contents of a specific memory location to the processor • The memory contents remain unchanged • To start a load operation • Processes sends the address of the desired location to memory • Request that its contents be read • The memory reads the data and sends to the processor www.bookspar.com | Website for students | VTU NOTES Memory operations Store operation - • Store operation transfers an item of information from the processor to a specific memory location • Destroys the former contents of that memory location • Processor needs to send the address of the desired memory location and also the data to be written into that location www.bookspar.com | Website for students | VTU NOTES Instructions and Instruction Sequencing • Tasks that are carried out by a computer consists of a sequence of small steps • Eg., add two numbers, test for a particular condition, read a character from keyboard, display a character on screen • A computer must have instructions capable of performing four types of operations • Data transfers between the memory and the processor registers • Arithmetic and logic operations on data • Program sequencing and control • I/O transfers www.bookspar.com | Website for students | VTU NOTES Register transfer notation Used to describe transfer of information from one location in the computer to another Possible locations are memory locations, processor registers, and registers in the I/O subsystem To identify a location Symbolic name standing for its hardware binary address Eg., name of memory locations – LOC,A,VAR2 etc Name of registers – R0,R5 Name of I/O registers – DATAIN Contents of a location denoted by placing square brackets around the name R1 [LOC] means contents of memory location LOC are transferred into processor register R1 R3 [R1] + [R2] ? www.bookspar.com | Website for students | VTU NOTES Assembly language notation • Used to represent machine instructions and programs • Example • To perform the data transfer R1 [LOC] the statement is Move LOC,R1 • Old contents of register R1 are overwritten but contents of LOC unchanged • R3 [R1] + [R2] is denoted by statement ? www.bookspar.com | Website for students | VTU NOTES Basic Instruction Types • A high level language program command C = A + B adds the contents of variables A and B and stores the result in variable C • After compilation, the three variable A,B and C are assigned distinct locations in memory • The contents of these locations represent the value of the three variables • The action is C [A] + [B] • Contents of A and B locations are fetched from memory and transferred into processor where the computation is performed • Result is then sent back to the location C www.bookspar.com | Website for students | VTU NOTES Accomplish C=A+B using Single Machine Instruction The instruction contains memory addresses of 3 operands – A,B and C Add A,B,C A and B are source operands C is destination operand Add is the operation to be performed Operation Source1,Source2, Destination If k bits are needed to specify memory address of each operand In addition to the bits needed to denote Add operation we need 3k bits more For a modern processor with 32-bit address space,a 3-address instruction is too large to fit in one word for a reasonable wrodlength www.bookspar.com | Website for students | VTU NOTES Accomplish C = A + B using two-address instructions Operation Source, Destination Eg., Add A,B which performs the operation B [A] + [B] When sum is calculated result is sent to memory replacing original contents of location B We cannot use a single two-address instruction as we don’t want to destroy the contents of A or B Solution? Use a instruction which copies contents of one memory location to another Move B,C performs the operation C [B] leaving contents of B unchanged Actually it only “copies” not “moves” Final solution is Move B,C Add A,C www.bookspar.com | Website for students | VTU NOTES Accomplish C = A + B using one-address instructions Even two-address instructions will not fit into one single word of memory Use one-address instruction Second operand , whenever required, is present in a unique location Eg., usage of accumulator, a processor register Add A means Add the contents of memory location A to the contents of accumulator register and place the sum back into the accumulator Load A Copies contents of memory location A into accumulator Store A Copies contents of accumulator to memory location A Solution? www.bookspar.com | Website for students | VTU NOTES Contd… • Load A • Add B • Store C • Operand specified may be source or destination depending on the instruction • For load it is source, • For store it is destination www.bookspar.com | Website for students | VTU NOTES Accomplish C = A + B using one-address instructions, and General purpose registers • Most modern computers have 32 General Purpose Registers or more • Only 5 bits sufficient to address 32 GPRs. How? • Registers are used to store data temporarily • Since access time to registers is much less than memory frequent access to memory is reduced hence enhancing speed www.bookspar.com | Website for students | VTU NOTES Accomplish C = A + B using one-address instructions, and General purpose registers • If Ri is a GPR • Load A,Ri • Store Ri,A • Add A,Ri are generalizations for the single-accumulator case • Data transfer instruction - Move • When we want to move from one place to another. • A single instruction Move can be used in place of Load and Store • Move Source, Destination • Move A, Ri is same as Load A,Ri • Move Ri,A is same as Store Ri,A www.bookspar.com | Website for students | VTU NOTES Contd • If artihmetic operations are allowed only on operands in processor registers then to achieve C = A + B • Move A,Ri • Move B,Rj • Add Ri,Rj • Move Rj,C • If one operand can be in memory but other must be in register then • Move A,Ri • Add B,Rj • Move Rj,C www.bookspar.com | Website for students | VTU NOTES Zero-Address instructions • Locations of all operands defined implicitly • Machines which store operands in a structure called pushdown stack • Instructions does not specify any memory address www.bookspar.com | Website for students | VTU NOTES Instruction execution and straight line sequencing • Assumptions Begin execution here Address i i +4 i +8 Contents Move Add Move A,R0 B,R0 R0,C 3-instruction program segment • GPRs • One addr insts • Wordlength 32bits A Data for the program B • Byte addressable • Full address in C • Single word instruction Figure 2.8. • The three insts at • i, i + 4, i + 8 A program for C [A] + [B]. www.bookspar.com | Website for students | VTU NOTES Instruction execution and straight line sequencing • PC holds address of instruction to be executed next • To begin execution • place the address of first inst to be executed in PC • Processor control circuits use info in PC to fetch and execute instructions, one at a time, in order of increasing addresses • This is called as Straight-line sequencing • During the execution of each instruction, PC is incremented by 4 www.bookspar.com | Website for students | VTU NOTES Instruction execution and straight line sequencing • Execution is two phase • Instruction Fetch • Instruction is fetched from memory location whose address in PC • This instruction is placed in IR • Instruction Execute • IR is examined to determine which operation is to be performed • Specified operation is then performed by processor • Involves fetching operands from memory or processor registers, performing arithmetic or logic operations, storing results in destination • At some point during this two-phase, the contents of PC is advanced to point to next instruction www.bookspar.com | Website for students | VTU NOTES Branching • Branch instruction load a new value to PC than the address of next immediate instruction following the branch instruction • This new address is called branch target • A conditional branch instruction causes branch only if a specified condition is satisfied Eg., Branch>0 LOOP www.bookspar.com | Website for students | VTU NOTES i i + 4 i + 8 i + 4n - 4 i + 4n SUM NUM1 NUM2 NUM n Figure 2.9. Move Add Add Add Move NUM1,R0 NUM2,R0 NUM3,R0 • • • NUM n ,R0 R0,SUM • • • • • • A straight-line program for adding n numbers. www.bookspar.com | Website for students | VTU NOTES Move Clear LOOP Program loop N,R1 R0 Determine address of "Next" number and add "Next" number to R0 Decrement Branch>0 Move SUM N NUM1 NUM2 NUM n Figure 2.10. R1 LOOP R0,SUM • • • n • • • Using a loop to add n numbers. www.bookspar.com | Website for students | VTU NOTES Assignment to be submitted on Thursday Express the following signed numbers in 2’s complement notation and perform addition and subtraction. State whether overflow occurs or not 4-bit notation 2&3, 5 & -6, -7 & 6, -8 & -3, 7 & 4 5-bit notation 12 & 3, 7 & -7, -6 & 14, -10 & -4, 12 & 8 Represent the following numbers in 32-bit Big-endian and Little-endian memory organization 81234561 -81234561 www.bookspar.com | Website for students | VTU NOTES Indirection and pointers • Indirect mode – the Effective address of the operand is the contents of a register or memory location whose address appears in the instruction • The register of memory location that contains the address of an operand is called a pointer • Analogy of treasure hunt • Instead of finding the treasure, we find the address where we find the treasure • By changing the contents of register R1 or location A in the following figure, the same add instruction fetches different operands to add to register R0. www.bookspar.com | Website for students | VTU NOTES Add (R1),R0 Add (A),R0 Main memory B R1 Operand B Register (a) Through a general-purpose register A B B Operand (b) Through a memory location Figure 2.11. Indirect addressing. www.bookspar.com | Website for students | VTU NOTES Indirect addressing logic for the program of adding n numbers using loop Address LOOP Contents Move Move Clear Add Add Decrement Branch>0 Move N,R1 #NUM1,R2 R0 (R2),R0 #4,R2 R1 LOOP R0,SUM Initialization Figure 2.12. Use of indirect addressing in the program of Figure 2.10. www.bookspar.com | Website for students | VTU NOTES INDEXED ADDRESSING Add 20(R1),R2 1000 1000 R1 20 R1 20 = offset 1020 Operand (a) Offset is given as a constant Add 1000(R1),R2 1000 20 = offset 1020 Operand (b) Offset is in the index register Figure 2.13. Indexed addressing. www.bookspar.com | Website for students | VTU NOTES n Student ID Test 1 Test 2 N LIST LIST + 4 LIST + 8 LIST + 12 LIST + 16 Test 3 Student ID Test 1 Test 2 Test 3 • • • Figure 2.14. A list of students' marks. Student 1 Student 2 www.bookspar.com | Website for students | VTU NOTES LOOP Move #LIST,R0 Clear R1 Clear R2 Clear R3 Move N,R4 Add 4(R0),R1 Add 8(R0),R2 A dd 12(R0),R3 Add #16,R0 Decrement R4 Branch>0 LOOP Move R1,SUM1 Move Move R2,SUM2 Note: contents of R0, which is used as indexed register, are not changed when it is used in indexed addressing mode to access test scores. Contents of R0 change only in last Add instruction, to move from one student record to the next R3,SUM3 Figure 2.15. Indexed addressing used in accessing test scores in the list in Figure 2.14. www.bookspar.com | Website for students | VTU NOTES Indexed addressing contd… • Several variations of the basic form of indexed addressing provide efficient access to memory operands • A second register may be used to contain the offset X, called as • • • • • • based indexed addressing mode Denoted as ( Ri, Rj ) Effective address is the sum of contents of Ri and Rj Second register is called base register. Provides more flexibility to the user Eg., suppose, in the previous example, instead of only 3 items, each student record contain a large no of items, say k We can replace the three Add instructions by a single instruction inside a second loop www.bookspar.com | Website for students | VTU NOTES Indexed addressing contd… • Problem • The list of student marks shown in prev figure 2.14, is changed to contain j test scores for each student. Assume that there are n students. Write an assembly language program for computing the sums of the scores on each test and store these sums in the memory word locations at addresses SUM, SUM + 4, SUM + 8,…. The number of tests, j, is larger than the number of registers in the processor. Use two nested loops, the inner loop should accumulate the sum for a particular test, and the outer loop should run over the number of tests, j. assume that j is stored in memory location J. www.bookspar.com | Website for students | VTU NOTES Solution www.bookspar.com | Website for students | VTU NOTES Indexed addressing mode contd.. • based indexed addressing mode with offset • Uses two registers plus a constant • X( Ri, Rj ) - Effective address is the sum of the constant X and the contents of registers Ri and Rj • This mode implements 3-Dimensional array www.bookspar.com | Website for students | VTU NOTES Relative addressing • Till now for index mode, registers we used are general purpose • • • • registers A useful variation of this is to use Program Counter PC instead of a general purpose register X(PC) – to address a memory location that is X bytes away from the location presently pointed to by the program counter Relative mode- the effective address is determined by the index mode using the program counter in place of the general-purpose register Ri. MOST common use is to specify the target address in branch instructions • Eg., Branch>0 LOOP • If branch condition is true, the program execution goes to branch target location identified by name LOOP • Can compute this location by specifying it as an offset from the current value of the program counter. www.bookspar.com | Website for students | VTU NOTES Example for relative addressing mode Address LOOP Contents Move Move Clear Add Add Decrement Branch>0 Move N,R1 #NUM1,R2 R0 (R2),R0 #4,R2 R1 LOOP R0,SUM Initialization Assume 4 instructions starting from LOOP are located at memory locations 1000,1004,1008 & 1012. Updated contents at the time branch target address is generated is 1016. to branch to location LOOP(1000), the offset value needed is X = -16 www.bookspar.com | Website for students | VTU NOTES Additional modes • Autoincrement and autodecrement mode – useful for accessing data items in successive locations in the memory • Autoincrement mode – • The effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to next element in the list • (Ri)+ • The increment is 1 for byte-sized operands, 2 for 16-bit operands and 4 for 32-bit operands. Usually size of operand is specified in the instruction www.bookspar.com | Website for students | VTU NOTES Autoincrement addressing logic for the program of adding n numbers using loop LOOP Move Move Clear Add Decrement Branch>0 Move N,R1 #NUM1,R2 R0 (R2)+,R0 R1 LOOP R0,SUM Initialization Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12. www.bookspar.com | Website for students | VTU NOTES Autodecrement mode • The contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand • Denoted by –(Ri) • Operands are accessed in descending address order. • The way the autoincrement and autodecrement modes are specified in very useful when implementing an important data structure called a stack. • Always we can use two instructions to perform the functionality of autoincrement and autodecrement mode www.bookspar.com | Website for students | VTU NOTES ASSEMBLY LANGUAGE • Machine instructions are represented by patterns of 0s and 1s • Such patterns are awkward to deal when discussing or preparing programs • Hence, usage of symbolic names to represent the patterns • Such symbolic acronyms( short forms) is called as mnemonics • A complete set of symbolic names and rules for their use constitute a programming language, referred to as assembly language • The set of rules for using the symbolic names is called as syntax of the language www.bookspar.com | Website for students | VTU NOTES ASSEMBLY LANGUAGE • Programs written in an assembly language can be automatically translated into a sequence of machine instructions by a program called an assembler. • The user program in its original form is called as source program • The assembled machine language program is called object program • The assembly language for a given computer may or may not be case sensitive www.bookspar.com | Website for students | VTU NOTES ASSEMBLY LANGUAGE A move instruction is written as MOVE R0,SUM The mnemonic MOVE represents the binary pattern, or OP code, for the operation performed by the instruction The assembler translates this mnemonic into the binary OP code that the computer understands OP-code followed by at least one blank space character Then the information that specifies the operands is given In above example , source operand is in register R0 Followed by specification of the destination operand – separated from source operand by a comma, with no intervening blanks In above example destination operand is in memory location that has its binary address represented by name SUM www.bookspar.com | Website for students | VTU NOTES ASSEMBLY LANGUAGE • Since there are several possible addressing modes for specifying operand locations, the assembly language must indicate which mode is being used. • # sign indicates immediate operand ( eg., ADD #5,R3) • In some assembly languages the immediate addr mode is intended in the OP-code mnemonic( eg., ADDI 5,R3) • Indirect addressing mode is usually specified by putting parentheses around the name denoting pointed operand. • If number 5 is to be placed in a memory location whose address is held in register R2, it is specified as MOVE #5,(R2) www.bookspar.com | Website for students | VTU NOTES ASSEMBLER DIRECTIVES In addition to providing mechanisms for representing instructions in a program, the assembly language allows programmer to specify other information needed to translate the source program to object program Eg., if name SUM is used to represent value 200, it can be conveyed to assembler as SUM EQU 200 This statement will not appear in the object program.. Rather informs the assembler that the name SUM is to be replaced by the value 200 Such statements are called as assembler directives Eg., ORIGIN – where in the memory should the data/instruction block that follows be placed DATAWORD – load the location with specified value RETURN – identifies the point at which execution of the program must be terminated. Assembler returns control to OS by inserting an appropriate machine instruction LOOP www.bookspar.com | Website for students | VTU NOTES 100 104 Move Move N,R1 #NUM1,R2 108 112 116 Clear Add Add R0 (R2),R0 #4,R2 120 124 128 132 Decrement Branch>0 Move R1 LOOP R0,SUM SUM N 200 204 NUM1 NUM2 208 212 NUM n Memory address label Assembler directives SUM N NUM1 Statements that generate machine instructions 100 Assembler directives START LOOP Operation Addressing or data information EQU 200 ORIGIN 204 DATAWORD 100 RESERVE 400 ORIGIN 100 MOVE N,R1 MOVE #NUM1,R2 CLR R0 ADD (R2),R0 ADD #4,R2 DEC R1 BGTZ LOOP MOVE R0,SUM RETURN END START 604 Fig2.17.Memory arrangement for program in Fig 2.12. Figure 2.18. Assembly language representation www.bookspar.com | Website for students | VTU NOTES Any statement that results in instructions or data being placed in memory location may be given a memory address label. Label is assigned the value equal to the address of that location Memory address label Assembler directives SUM N NUM1 Statements that generate machine instructions Assemblerdirectives START LOOP Operation EQU ORIGIN DATAWORD RESERVE ORIGIN MOVE MOVE CLR ADD ADD DEC BGTZ MOVE RETURN END Addressing or data information 200 204 100 400 100 N,R1 #NUM1,R2 R0 (R2),R0 #4,R2 R1 LOOP R0,SUM START Figure 2.18. Assembly language representation for the program in Figure 2.17. www.bookspar.com | Website for students | VTU NOTES CONTD…. • Most assembly languages require statements in a source program to be written in the form • Label • • • • Operation Operand(s) Comment Label – is optional and is associated with memory address where the machine language instruction or the data items are stored Operation field contains the OP-code mnemonic of the desired instruction or assembler directive Operand field contains addressing information for accessing one or more operands, depending on the type of instruction Comment field is ignored by the assembler program • Used for documentation purposes www.bookspar.com | Website for students | VTU NOTES ASSEMBLY and EXECUTION OF PROGRAMS ASSEMBLER replaces All symbols denoting operations and addressing modes with binary codes All names and labels with their actual values. In a branch instruction, branch target is not replaced by actual address. Usually it uses relative addressing mode. Assembler computes branch offset, and puts into the machine instruction The assembler keeps track of all names and the numerical values that correspond to them in a symbol table When a name appears a second time, it is replaced with its value from the table. A problem arises if some name appears before it is given a value. Eg., forward branching. Solution is to scan through the program twice – once to collect the values of all names and second time to substitute values for all names from symbol table. Such an assembler is called as TWO-PASS ASSEMBLER www.bookspar.com | Website for students | VTU NOTES ASSEMBLY and EXECUTION OF PROGRAMS Assembler stores object program on a magnetic disk The object program must be loaded into memory before it is executed A utility program called loader does this. For this loader must already be in memory Loader must know the length of the program and the address in the memory where it will be stored Assembler usually places this info in a header preceding the object code When the object program begins execution, it proceeds to completion unless there are errors. To help debugging, system software usually includes a debugger program www.bookspar.com | Website for students | VTU NOTES NUMBER NOTATIONS • Can use either decimal, or binary or hexadecimal notation • Eg., ADD #93, R1 • This is in decimal • In binary – ADD #%01011101,R1 • Here % tells that we are using a binary number • In hexadecimal – ADD #$5D, R1 • Here $ denotes the usage of hexadecimal www.bookspar.com | Website for students | VTU NOTES Questions • Mention the steps assembler performs in order to convert a source program into object program • What is symbol table? Why do we need it? How does the assembler populate symbol table? • What is a loader? What information must assembler pass on to loader to perform its function? How does the assembler do it? www.bookspar.com | Website for students | VTU NOTES BASIC INPUT/OUTPUT OPERATIONS Till now we have assumed that the data operated in stored in memory already. Now, let’s see how data transfer takes place between computer and outside world The I/O operations are very important and the way they are done can significantly affect the performance of the computer The rate of data transfer from the keyboard to a computer is limited by the typing speed of the user Few characters per second The rate of output transfers from the computer is determined by the rate at which characters can be transmitted over the link between the computer and display device. Typically several thousand characters per second Both are much slower than the speed of processor Can execute many millions of instructions per second Hence need for the mechanisms to synchronize the transfer of data between them. www.bookspar.com | Website for students | VTU NOTES Solution to speed disparity • On output, the processor sends the first character and then waits for a signal from the display that character has been received • Then it sends the second character and so on • For input, the processor waits for a signal indicating that a character key has been struck and that its code is available in some buffer register associated with keyboard • Then only will processor proceed to read the code SIN Key board SOUT Display Figure 2.19 Bus connection for processor , keyboard, and display . www.bookspar.com | Website for students | VTU NOTES DATAIN/DATAOUT – buffer registers SIN/SOUT – status control flags The striking of a key on keyboard does not automatically cause the corresponding character to be displayed on the screen! One block of instructions in I/O program causes the character to be transferred to processor and another block of instructions will cause the character to be displayed on the screen www.bookspar.com | Website for students | VTU NOTES How data is read? • The technique used is called program – controlled I/O • Striking a key stores the corresponding character code in • • • • a 8-bit buffer register called DATAIN. To inform the processor that a valid character is in DATAIN, a status control flag SIN is set to 1. A program monitors SIN, and when SIN is set to 1, the processor reads the contents of DATAIN. When the character is transferred to the processor, SIN is automatically cleared to 0. When a second character is read, SIN is again set to 1 and the process repeats www.bookspar.com | Website for students | VTU NOTES How data is displayed? • A buffer register DATAOUT and status control flag SOUT is used. • When SOUT is 1, display is ready to receive a character • Under the control of a program, ( hence program – controlled I/O), the processor monitors SOUT and when SOUT is set to 1, the processor transfers a character code to DATAOUT • The transfer of character to DATAOUT clears SOUT to 0. • When the display is ready to receive a second character, again SOUT is set to 1. • SIN , SOUT , DATAIN, DATAOUT are part of circuitry called as device interface, connected to processor through bus www.bookspar.com | Website for students | VTU NOTES Programs for I/O • Assume that SIN is set to 0 initially and SOUT is set to 1. • This initialization is performed by device control circuits • How to refer to the buffers DATAIN and DATAOUT? • Many computers use arrangement called as memory-mapped I/O • Some memory address values are used to refer to peripheral device buffer registers such as DATAIN and DATAOUT • Thus no special instructions required to access the contents of these registers • Eg., Movebyte DATAIN, R1 moves the contents of keyboard character buffer DATAIN to R1 • Similarly, Movebyte R1, DATAOUT • The status flags SIN and SOUT are automatically cleared when the buffer registers are referenced • Movebyte signifies that the operand is a byte, not a word www.bookspar.com | Website for students | VTU NOTES Programs for I/O • It is common to include SIN and SOUT in device status registers, which have distinct memory addresses • Assume that the status registers are INSTATUS and OUTSTATUS respectively for input and output • Also assume that SIN and SOUT are referred by bit3 in the registers. • Read operation • READWAIT Testbit • • • Write operation • WRITEWAITTestbit • • #3, INSTATUS Branch=0 READWAIT Movebyte DATAIN,R1 #3,OUTSTATUS Branch=0 WRITEWAIT Movebyte R1,DATAOUT www.bookspar.com | Website for students | VTU NOTES Move #LOC,R0 READ TestBit Branch=0 MoveByte #3,INSTATUS READ DATAIN,(R0) ECHO TestBit Branch=0 MoveByte #3,OUTST ATUS ECHO (R0),DATAOUT Compare #CR,(R0)+ Branch 0 READ Initialize pointer register R0 to pointto the address of the firstlocation in memory wherethe characters are tobe stored. Wait for a character tobe entered in the keyboardbuffer DATAIN. Transferthe character fromDATAIN into the memory(this clears SIN to 0). Wait for the display to become ready. Move thecharacterjust read to the display buffer register(this clearsSOUT to 0). Checkif the character just read is CR (carriage return). If it is not CR, then branch bac k and read another character. Also, increment the pointer to store the next character. Figure 2.20. A program that reads a line of characters and displays it. www.bookspar.com | Website for students | VTU NOTES STACKS and QUEUES • Stacks mainly used to organize control and information linkage between main program and the subroutine • A stack is a list of elements, usually words or bytes, with the accessing restriction that elements can be added or removed at one end of the list only. • This end is called as the top of stack • The other end is called as bottom • Hence also called as pushdown stack • Eg., a pile of trays in a cafetaria • Storage mechanism is also referred by LIFO ( Last-in-First-Out) • Push – put an element on top of stack • Pop – remove an element from top of stack www.bookspar.com | Website for students | VTU NOTES Problem • In a memory, we can store a total of 2k words. The memory is byte-addressable. How many bits are required in the address space for this memory, to address all the bytes? Assume the word length to be 16 bits. www.bookspar.com | Website for students | VTU NOTES 0 Stack pointer register SP • • • - 28 Current top element 17 739 Stack BOTTOM Normal practice is stack grows in the direction of decreasing memory addresses k 2 - 1 • • • 43 • • • Figure 2.21. A stack of words in the memory. Bottom element Stack pointer(SP) – is a processor register used to keep track of the address of the top element of stack www.bookspar.com | Website for students | VTU NOTES Push and Pop operations on Stack • Stack pointer keeps track of the address of the top of stack • To Push an element • Subtract #4,SP • Move NEWITEM,(SP) • To Pop an element • Move (SP),ITEM • Add #4,SP • If processor support autoincrement and autodecrement • Push Move NEWITEM,-(SP) • Pop Move (SP)+,ITEM www.bookspar.com | Website for students | VTU NOTES Stacks contd… • Care has to be taken that stack is not popped when empty and pushed when full • Usage of Compare instruction • Compare src,dst • [dst] – [src] and affect flags accordingly • eg/., BOTTOM – at addres 2000 • Till location 1500 www.bookspar.com | Website for students | VTU NOTES SAFEPOP Compare Branch> 0 #2000,SP EMPTYERROR Move (SP)+,ITEM Check to seeif the stack pointer contains an addressvaluegreaterthan 2000. If it does,the stack is empty . Branch to the routine EMPTYERROR for appropriate action. Otherwise,pop the top of the stack into memory location ITEM. (a) Routine for a safe pop operation SAFEPUSH Compare Branch 0 #1500,SP FULLERROR Move NEWITEM,– (SP) Check to seeif the stack pointer contains an addressvalueequal to or less than1500. If it does, the stack is full. Branch to the routine FULLERROR for appropriateaction. Otherwise,push the element in memory location NEWITEM onto the stack. (b) Routine for a safe push operation Figure 2.23. Checking for empty and full errors in pop and push operations. www.bookspar.com | Website for students | VTU NOTES Queue – First In First Out List Data elements are inserted in memory at the increasing order of memory addresses i.e., at the back of Queue. Data elements are retrieved from memory at the decreasing order of memory addresses i.e. from the front end of Queue. Operations such as QINSERT and QDELETE can be performed on a queue to insert and delete & element respectively. A Queue consisting of 6 elements may appear as follows: www.bookspar.com | Website for students | VTU NOTES Difference between implementation of stacks and queues • Stacks • One end of a stack is fixed ( bottom ), while the other end rises and falls as data are pushed and popped. Hence a single pointer is needed to point to the top of stack at any given time. • A stack is assigned a fixed amount of space in memory. • Queues • Both ends of queue move to higher addresses as data are added at the back and removed from the front. So two pointers are needed to keep track of the two ends of the queue. • Without further control, a queue would continuously move through the memory of a computer in the direction of higher addresses. • One way to limit the queue to a fixed region in memory is to use a circular buffer. www.bookspar.com | Website for students | VTU NOTES SUBROUTINES • In a given program, it is many times needed to perform a particular subtask on different data values. Such a sub task is called as subroutine • Eg., a subroutine to calculate sine function, or to sort a list of values in increasing or decreasing order • One copy of the instructions that constitute subroutine is placed in the memory, and any program that requires the use of subroutine branches to its starting location. • This branching to a subroutine is termed as calling the subroutine • The instruction which performs this is Call instruction • www.bookspar.com | Website for students | VTU NOTES SUBROUTINES - Linkage • After a subroutine has been executed, the calling program must resume execution continuing immediately after the instruction that called the subroutine. • This is performed by a Return instruction • Since a subroutine may be called from different places, we need to make provision to return to appropriate location • The location where the calling program resumes execution is the location pointed to by the updated PC while the Call instruction is being executed. • Hence, need to save the contents of PC by Call instruction to enable correct return. • The method in which computer calls and returns from subroutines is referred to as subroutine linkage method • Simplest way is to save the return address in a specific location, which may be a register dedicated to perform this function • Such a register is called as link register • When the subroutine completes its task, the Return instruction returns to the calling program by branching indirectly through the link register www.bookspar.com | Website for students | VTU NOTES Memory location Memory location Calling program 200 204 Call SUB next instruction Subroutine SUB 1000 first instruction Return 1000 PC 204 Link 204 Call Call instruction performs the following operations Figure 2.24. i. Store the contents of PC in link register ii. Branch to the target address specified by the instruction Subroutine linkage using a link register. Return Return instruction performs the following operation i. Branch to the address contained in link register www.bookspar.com | Website for students | VTU NOTES SUBROUTINES - NESTING AND PROCESSOR STACK • Subroutine nesting – it’s a practice where in one subroutine calls another subroutine. • In this case, the return address of the second call is also stored in link register, destroying its previous contents. • Hence, need to save the contents of link register in some other location before calling another subroutine. • Else the return address of first subroutine is lost • Subroutine nesting can be carried out to any depth. • Last subroutine that is called completes computations and returns to the subroutine which called it. • Hence return addresses are generated and used in a last-in-first-out order. • Hence return addresses can be pushed onto a stack. • Many processors do this automatically as one of the operations performed by call instruction • A special pointer called stack pointer, points to a stack called processor stack. • the call instruction pushes the contents of the PC onto the processor stack and loads the subroutine address into the PC. • The return instruction pops the return address from the processor stack into the PC www.bookspar.com | Website for students | VTU NOTES Subroutines - PARAMETER PASSING • When calling a subroutine, a program must provide to the subroutine the parameters, (operands or their addresses), to be used in the computation • The subroutine returns other parameters ( the results of computation) back. • This exchange of information between calling program and subroutine is called as parameter passing • Can be done in several ways • Can place the parameters in registers or memory locations • Placing in processor registers in highly efficient and straight forward • No of parameters that can be passed is limited by the number of general purpose registers available • The parameters may also be placed on processor stack. • Highly flexible and can handle a large no of parameters www.bookspar.com | Website for students | VTU NOTES Addition of N numbers in a loop using subroutines. Parameters are passed through registers Calling program Move Move Call Move .. . N,R1 #NUM1,R2 LISTADD R0,SUM R1 servesas a counter. R2 pointsto thelist. Call subroutine. Save result. Clear Add Decrement Branch>0 Return R0 (R2)+,R0 R1 LOOP Initialize sumto 0. Add entry from list. Subroutine LISTADD LOOP Return to calling program. Figure 2.25. Program of Figure 2.16 written as a subroutine; parameters passed through registers. www.bookspar.com | Website for students | VTU NOTES Program to add a list on n numbers written as a subroutine. Parameters are passed through processor stack NOTE : parameter passing either by pass by value or pass by reference n – is passed by value (actual value is passed) NUM1 – passed by reference. address is passed ( not the actual entries of the list but the address of first element is passed Figure 2.26. Program of Figure 2.16 written as a subroutine; parameters passed on the stack. www.bookspar.com | Website for students | VTU NOTES Subroutines – Stack Frame • The locations which will be used by the subroutine on stack for private work, constituting a private work space for the subroutine, which is created at the time the subroutine is entered and freed up when the subroutine returns control to the calling program, is called as stack frame. • Can also allocate space for local memory variables www.bookspar.com | Website for students | VTU NOTES Stack frames • In addition to stack pointer, it is useful to have another additional pointer register, called frame pointer (FP) • The local variables are local to the subroutine, hence can be allocated space in stack frame associated with the subroutine • FP points to the location just above the return address • Contents of FP remain fixed throughout the execution of subroutine www.bookspar.com | Website for students | VTU NOTES Move FP,-(SP) Move SP,FP SP (stack pointer) saved [R1] saved [R0] localvar3 localvar2 localvar1 FP (frame pointer) saved [FP] Return address Subtract #12,SP Stack frame for called subroutine param1 Access parameters using index addr mode. 8(FP), 12(FP) Local variables canFigure 2.27. be accessed using addresses -4(FP), -8(FP) param2 param3 param4 Old TOS (top-of-stack) A subroutine stack frame example. The calling program is responsible for removing parameters from stack frame, some of which may be results passed back by the subroutine www.bookspar.com | Website for students | VTU NOTES Stack frames for nested subroutines • Stack is a proper data structure for holding return addresses when subroutines are nested • Complete stack frames for nested subroutines build up on the processor stack • Saved contents of FP in the current stack frame are the frame pointer contents for the stack frame of the subroutine that called the current subroutine www.bookspar.com | Website for students | VTU NOTES Reading Assignment : ( not to be submitted ) • Read and understand the program and the stack frame structure that follows. This is the program with nested subroutines and associated stack frame ( pg 78-80 in text) www.bookspar.com | Website for students | VTU NOTES Memory lo cation Main Figure shows only flow of control and data between subroutines. Not the actual computations Instructions program 2000 2004 2008 2012 2016 2020 First 2100 2104 2108 2112 3000 P ARAM2, – (SP) P ARAM1, – (SP) SUB1 (SP),RESUL T #8,SP Place parameters FP ,– (SP) SP ,FP R0 – R3, – (SP) 8(FP),R0 12(FP),R1 Sav e frame poin ter register. Load the frame poin ter. Sav e registers. Get first parameter. Get second parameter. Store result. Restore stack on stack. lev el. subroutine SUB1 2160 2164 Second .. . Mo v e Mo v e Call Mo v e Add next instruction .. . Commen ts Mo v e Mo v e Mo v eMultiple Mo v e Mo v e .. . Mo v e Call Mo v e .. . Mo v e Mo v eMultiple Mo v e Return P ARAM3, SUB2 (SP)+,R2 R3,8(FP) (SP)+,R0 (SP)+,FP – (SP) – R3 Place a parameter on stack. Pop SUB2 in to R2. result Place answ er on stack. Restore registers. Restore frame p oin ter register. Return to Main program. subroutine SUB2 Mo v e Mo v e Mo v eMultiple Mo v e .. . Mo v e Mo v eMultiple Mo v e Return FP ,– (SP) SP ,FP R0 – R1, – (SP) 8(FP),R0 Sav e frame p oin ter register. Load the frame p oin ter. Sav e registers R0 and R1. Get the parameter. R1,8(FP) (SP)+,R0 (SP)+,FP Place SUB2 result on stack. Restore registers R0 and R1. Restore frame p oin ter register. Return to Subroutine 1. – R1 Figure 2.28. Nested subroutines. www.bookspar.com | Website for students | VTU NOTES FP [R1] from SUB1 [R0] from SUB1 [FP] from SUB1 2164 param3 [R3] from Main FP [R2] from Main [R1] from Main [R0] from Main [FP] from Main 2012 Stack frame for second subroutine Stack frame for first subroutine param1 param2 Old TOS Figure 2.29. Stack frames for Figure 2.28. www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS • Instructions so far • Move • Load • Store • Clear • Add • Subtract • Increment • Decrement • Branch • Testbit • Compare • Call • Return Even this small set of instructions has a number of redundancies Eg., Load and Store instructions can be replaced by a single Move instruction Increment by Add and Decrement by Subtract instruction Clear by a Move ( moving zero ) www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS • Logic instructions • Not • Complement all the bits in destination operand • Not R0 ( complement all bits of R0) • Can get 2’s complement representation of a negative number • Not R0 ( R0 contains, say 3) • Add #1,R0 • Can get 2’s complement of a number by a single instruction • Negate R0 • Bitwise And , Or • Performs and & or operations bitwise • And #$FF000000,R0 • Problem : write a program which checks whether an entered 4letter word contains Z in the beginning. www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS • Answer • And $#FF000000, R0 • Compare #$5A000000,R • Branch=0 YES • And instruction is often used in practical programming tasks where all bits of an operand except for some specified field are to be cleared to zero • Problem: Write program to clear the bits b10 to b31 in a 4 byte word www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS – • Shift instructions Shift and Rotate instructions • For general operands we use logical shifts • For signed numbers, we use arithmetic shifts ( to preserve the sign of the number) • Logical Shifts • 2 instructions – for left shift and for right shift • LShiftL count, destination • LShiftR count, destination • Count can be given either as immediate operand or given inside a processor register • Vacated positions are filled with zeros • The bits shifted out are passed through the Carry flag, C, and then dropped www.bookspar.com | Website for students | VTU NOTES C R0 0 before: 0 0 1 1 1 0 . . . 0 1 1 after: 1 1 1 0 . . . 0 1 1 0 0 (a) Logical shift left LShiftL 0 #2,R0 R0 C before: 0 1 1 1 0 . . . 0 1 1 0 after: 0 0 0 1 1 1 0 . . . 0 1 (b) Logical shift r ight LShiftR #2,R0 R0 C before: 1 0 0 1 1 . . . 0 1 0 0 after: 1 1 1 0 0 1 1 . . . 0 1 (c) Ar ithmetic shift r ight AShiftR #2,R0 Figure 2.30. Logical and arithmetic shift instructions. www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS – Shift and Rotate instructions • Digit packing • 2 decimal digits represented in ASCII are located in memory at byte locations LOC and LOC + 1 • Represent each of these digits in 4-bit BCD and store in a single byte location PACKED (the result is said to be in packed-BCD format) • Hint: rightmost 4 bits of the ASCII code for a decimal digit correspond to the BCD code for the digit www.bookspar.com | Website for students | VTU NOTES Move MoveByte LShiftL MoveByte And Or MoveByte #LOC,R0 (R0)+,R1 #4,R1 (R0),R2 #$F,R2 R1,R2 R2,PACKED R0 points to data. Load first byte into R1. Shift left by 4 bit positions. Load secondbyte into R2. Eliminate high-order bits. ConcatenatetheBCD digits. Store the result. Figure 2.31. A routine that packs two BCD digits. www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS – Shift and Rotate instructions • Arithmetic Shifts • Shifting a number one bit left is same as multiplying the number by 2 • Overflow may occur • Shifting right is equivalent to dividing the number by 2 • Reminder is lost • On a right shift sign-bit must be repeated as the fill in bit for the vacated position, main difference between Arithmetic shift and logical shift www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS – Shift and Rotate instructions • Rotate instructions • 4 in number • Rotate left without Carry – RotateL • Rotate left with Carry – RotateLC • Rotate right without Carry – RotateR • Rotate right with Carry - RotateRC www.bookspar.com | Website for students | VTU NOTES C R0 before: 0 0 1 1 1 0 . . . 0 1 1 after: 1 1 1 0 . . . 0 1 1 0 1 (a) Rotate left without carry RotateL C #2,R0 R0 before: 0 0 1 1 1 0 . . . 0 1 1 after: 1 1 1 0 . . . 0 1 1 0 0 (b) Rotate left with carry RotateLC #2,R0 R0 C before: 0 1 1 1 0 . . . 0 1 1 0 after: 1 1 0 1 1 1 0 . . . 0 1 (c) Rotate r ight without carr y RotateR #2,R0 R0 C before: 0 1 1 1 0 . . . 0 1 1 0 after: 1 0 0 1 1 1 0 . . . 0 1 ight with carr y (d) Rotate r RotateRC #2,R0 Figure 2.32. Rotate instructions. www.bookspar.com | Website for students | VTU NOTES ADDITIONAL INSTRUCTIONS – Shift and Rotate instructions • Multiplication and Division • MultiplyRi,Rj • Product can be as large as 2n bits for 2 n-bit numbers • Answer will not necessarily fit in Rj • Lower order bits in Rj, higher order bits in Rj+1 • Some systems provide Divide Ri ,Rj • Rj/Ri and quotient in Rj • May place remainder in Rj+1 • Computers which do not have divide and multiply instructions can implement same using basic instructions like add, subtract, shift and rotate www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • Till now we have not used acronyms for instructions because they are specific to a particular processor in market ( eg., we used Move instead of MOV ) • To be executed, an instruction must be encoded in a compact binary pattern. Such encoded instructions are properly referred to as machine instructions • The instructions that use symbolic names and acronyms are called as assembly language instructions, which are converted to machine instructions using assembler program www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • The type of operation to be performed and the type of operands used is specified using an encoded binary pattern referred to as the OP code for the given instruction • Suppose 8 bits are assigned for OP code to specify upto 256 different instructions • If we assume that word length is 32-bits and if we want to fit an entire instruction into a single memory word, then we are left with 24 bits to specify rest of the information • Eg., Add R1,R2 has to specify the registers R1 and R2, in addition to the OP code • If system has 16 registers, then 4 bits are required to identify each register and some additional bits to specify that we are using register addressing mode www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • Move 24(R0) ,R5 • 16 bits to denote OP code, 2 registers, some bits to express that source operand uses index addressing mode and that index value is 24 • Suppose 3 bits are used to specify addressing mode • We need 6 bits – to denote the chosen addressing mode for both source and destination operands • 32 – ( 16+6) = 10 bits left to give the index value ( signed number ) • Eg., LShiftR #2,R0 • Move #$3A, R1 how many bits left to specify immediate value? www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • Branch>0 LOOP • Here 8 bits for OP code. How many bits for Branch OFFSET? • What is the limit for the branch target address with respect to branch insrtuction? • Jump instruction - uses Absolute or Register Indirect mode to specify branch target www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • CISC processors use instructions that are complex and require more than a single word to specify the instruction • Consider instruction • Add LOC,R2 • Here 8 bits for OP code, 10 bits for addr mode and specifying the register, remaining 14 bits cannot hold a 32-bit address of the absolute addressing mode • Hence we need to go either for multiple word instruction • Or • Register Indirect • Load address of LOC to R3 • Add (R3),R2 www.bookspar.com | Website for students | VTU NOTES 8 7 7 10 OP code Source Dest Other info (a) One-word instruction OP code Source Dest Other info Memory address/Immediate operand (b) Two-word instruction OP code Ri Rj Rk Other info (c) Three-operand instruction Figure 2.39. Encoding instructions into 32-bit words. www.bookspar.com | Website for students | VTU NOTES ENCODING OF MACHINE INSTRUCTIONS • But how to load 32-bit address to register? • One way is to use indexed addressing mode to load the address into register ( for this need to place the address in a memory location close to the program) • Other option is to use Logical and Shift instructions – passing the address by parts • The restriction that the instruction must fit in a single word ( 32 bit here ) is the style of RISC machines • Places a restriction that all manipulation of data contained only in processor registers • Move (R3) ,R1 • Add R1,R2