Download AMICSA2016_EMFT_OHB_Bora

Development of a Digital Temperature
Transducer ASIC in a 28 nm FD-SOI CMOS
Process for a Spaceborne Low Power Sensor
Bus
P. P. Boraa, M. Ronerb, D. Borggrevea,
A. Hurnib, E. Isaa, L. Maurerc
aFraunhofer
EMFT, Munich, Germany
bOHB System AG, Oberpfaffenhofen, Germany
cUniversität
der Bundeswehr, Neubiberg, Germany
13.06.2016
This work is funded through project THINGS2DO under the ENIAC grant agreement number 621221 and the national grant agreement number 16ES0240.
© Fraunhofer
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
2
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
3
Background
Housekeeping in Geostationary Satellites
 where the satellite is pointing
 which parts are working properly
 what its temperature is
°C
Importance of temperature sensing
 Large temperature difference
Image Courtesy: NASA
 To support the onboard Thermal
© Fraunhofer
Control System
 Temperature requirements of
equipments for reliable operation
4
Source: spac0255, NOAA In Space Collection
Housekeeping Data tells:
Sensor
F
Sensor
C
A
Sensor
G
Background
Sensor
Interrogator
Sensor
I
Sensor
H
Conventional vs Serial Sensor Network
Current Star Topology
Sensor
B
Sensor
A
Sensor
D
Sensor
B
Sensor
E
Sensor
A
Sensor
F
Sensor
C
Sensor
G
Sensor
Interrogator
Future Bus Topology
Sensor
I
Sensor
H

Conventional
Network
FutureSensor
Bus Topology
 Star Sensor
topology
Sensor
D
B
Sensor
Lot of cables
A
 Extra weight
 Inflexible for future
Sensor
© Fraunhofer
Interrogator
Sensor
I
Sensor
F
Sensor
C
Sensor
G
Sensor
Interrogator
Sensor
I
Sensor
H
Digital
Temperature
Transducer ASIC
in 28 nm FD-SOI
 Hybrid Bus topology
Sensor
E
 Serial Bus line: reduction in wiring
 Electrical and fiber optical sensor
network
Sensor
G
Sensor
H
Sensor
E
Future Sensor Bus System
Sensor
F
Sensor
C
Sensor
D
5
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
6
28 nm FD-SOI Technology
Process Features
 Characteristics [1]
Source
Fully Depleted
Silicon Film

Low Cds and Ileakage

High Speed (LVT, Forward BB)

Low leakage (RVT, Reverse BB)

High Body-biasing tuning range and sensitivity [3]

Robust against latch-up
Front Gate
Drain
Gate Oxide
7 nm
25 nm
Buried Oxide (BOX)
Well
Back Gate
[2]
 Radiation tolerance
Image ©STMicroelectronics

Thin front oxide

Reduced sensitive volume

Robust against SEL

High TID tolerance due to 25 nm BOX
Bulk CMOS versus FD-SOI CMOS
Ionizing Particle
Ionizing Particle
BOX
Bulk transistor
[1] S. Shopov, S.P. Voinigescu, "Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function
of Backgate Bias", Compound Semiconductor Integrated Circuit Symposium (CSICs), 2014 IEEE
© Fraunhofer
[2] http://cmp.imag.fr/documents/doc/UTBB-FDSOI%20Design%20and%20Migration%20Methodology_.pdf
[3] S. Le Tual et al, “A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology”,
ISSCC2014
7
FD-SOI transistor
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
8
System Requirements
Temperature Range
-40 °C to +125 °C
Accuracy
±1 °C in [-20 °C, +20 °C] and ±3 °C outside
Measurement Resolution
0.1 °C
ADC Resolution
≥ 11 bits
SEU LET threshold
≥ 20 MeV∙cm²/mg
TID tolerance
≥ 300 krad
Interface type
Serial (I2C)
Lifetime
15 years in-orbit operation
© Fraunhofer
9
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
10
System Description
Sensor
Core
Timing and Control
VREF
Vin+
Signal
Conditioning
circuit
Analog
Decimation
∑Δ Modulator
MUX
Filter
Vin-
+
VPTAT
‒
ADC
+
‒ ΔVBE+
+
VBE2
VBE1
‒
‒
+
µ
VREF
Temperature sensing concept
© Fraunhofer
.
.
.
.
Digital
Interface
..
VREF = VBE2 + VPTAT
m·I1
Voltage (V)
I1
Serial I/O
External sensor
Inputs from
VPTAT
Biasing
Address
Temperature
Transducer
ASIC
Clock
Block Diagram
11
VBE2
VPTAT = α . (VBE2 - VBE1)
-40
+125 Temperature (°C)
System Description
Radiation Hardening
System-level
Circuit-level
• Optimal transistor sizing
• Offset-compensation
• Back gate biasing
• Redundancy techniques
FF1
Input
FF2
Voter
Output
FF3
Image ©STMicroelectronics
Device-level
Layout-level
• FD-SOI CMOS technology
• Placement of guard-rings
Cell
Image ©STMicroelectronics
© Fraunhofer
VSS
12
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
13
Demonstrator
AMBER1: Top Level
 Developed under THINGS2DO project
1800 µm
 Aim:
 Validate core design components
∑∆
 Validate process features (Body-biasing,
Passive devices)
BGR
DCO
SAR
LNA
 1.0 V (Core) and 1.8 V (I/O) Supplies
T. Line
 Features design blocks for:
DAC
Mixer
 ∑∆ Modulator, SAR ADC, DAC, LNA, DCO,
Mixer, Transmission line, Band Gap
Reference.
© Fraunhofer
1800 µm
 92 pins, QFN 100 package
14
Demonstrator
Sigma-Delta Modulator
 Modulator:
159 µm
 Operation voltage 1.0 V (nominal)
∑∆ Modulator
 Fully-differential
 1st order, discrete time
Modulator
Output
Vin+
 1-bit quantization
-
249 µm
 Bandwidth = 500 Hz
 fsampling
= 200 kHz
 Symmetrical Layout
OTA
 Operational Transconductance Amplifier
 DC Gain
= 65 dB
 Gain Bandwidth = 20 MHz
© Fraunhofer
15
Demonstrator
Sigma-Delta Modulator
VREF- VREF+
CLK
ϕ2.BS-
Vin
+
-
∑
+
-
∫
+
Vin
Dout
-
ϕ1
ϕ1
ϕ2
VCM
ϕ1
Cs
ϕ2.BS+
ϕ2
CCDS
CCDS
- +
-25 -
BS+
ϕ1
+ Ci
Current-mirror OTA [2]
Input Amplitude
1.0 VPP (½ Full Scale)
ENOB
7.14 bits
SINAD
44.78 dB
SNR
64.94 dB
SFDR
44.82 dB
Power
64 µW (1.0 V Supply)
-50 -
-75 -
102
Bandwidth = 500 Hz
103
104
-
-
-
-
-125 10
-
---100 -
105
(Hz)
[1] Enz, Christian C., and Gabor C. Temes. "Circuit techniques for reducing the effects of op-amp
imperfections: autozeroing, correlated double sampling, and chopper stabilization." Proceedings of the IEEE
84.11 (1996): 1584-1614.
© Fraunhofer
16
[2]Roh, Jeongjin, et al. "A 0.9-V 60-μW 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range." SolidState Circuits, IEEE Journal of 43.2 (2008): 361-370.
Dout
BS-
ϕ1
Correlated-double
Sampling (CDS) [1]
f_in = 121.07 Hz
Dynamic Comparator with
latch [2]
ϕ1
VREF+ VREF-
0 -6 -
Power (dB)
ϕ2.BS+
Cs
ϕ2.BS-
DAC
ϕ1 C
i
Agenda
 Background
 28 nm FD-SOI Technology
 System Requirements
 System Description
 Demonstrator
 Conclusion
© Fraunhofer
17
Conclusion

Digital Temperature Transducer ASIC:
 Sensing, data-conversion and communication

28 nm FDSOI CMOS Process:
 Reduced parasitics, back-gate biasing, good radiation tolerance

System Requirements:
 Up to ±1 °C accuracy in [-20 °C, +20 °C] with 0.1 °C resolution

Demonstrator: AMBER1 IC
 ∑∆ Modulator:1st order, discrete-time, correlated double sampling

Next Steps:
 Validate 1st order ∑∆ Modulator on AMBER1 IC
 Integrate sensor core and digital circuitry

Outlook:
 Digital intensive design: exploit low-power features of 28 nm FD-SOI CMOS process
 Further integration of components for space applications based on FD-SOI
© Fraunhofer
18
THANK YOU
© Fraunhofer