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An Ultra Low Power Wireless Micro-Sensor Node D. Daly, D. Finchelstein, N. Ickes, N. Verma, A. Chandrakasan Three custom chips optimized for microsensor applications: ADC DSP 8/12-bit SAR architecture 25 µW at 100 kS/s 16-bit RISC machine Custom instruction set C compiler (lcc) 1024-pt FFT accelerator 165 fJ/conversion step Self-calibrating latch Self-timed bit cycling Radio 916.5MHz, OOK, 1Mbps ~10m range RX: 0.5–2.6 nJ/bit TX: 3.8–9.1 nJ/bit 2.5 µs RX start-up time Chips fabricated in 0.18µm CMOS by National Semiconductor System Integration A complete acoustic sensor node Lithium battery Preamp ADC ADC I/F FFT accelerator SRAM Radio I/F CPU Microphone • Credit-card sized node • Discrete power regulators, acoustic front end FPGA Power Management/Regulation ADC RX BB RF PA • FPGA for radio clock/data recovery • All other functions performed by chipset Power Regulators Radio RX Antenna ADC DSP Microphone TX Antenna FPGA Example Application Benchmark Acoustic target classification Sample microphone Compute FFT Identify peaks Send to base station >< 1500 3.8 mW peak Power (µW) ~ 1000 Radio ADC 500 DSP 0 0 50 100 150 Time (ms) 200 250
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