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CS/EE 3700 : Fundamentals of
Digital System Design
Chris J. Myers
Lecture 5: Arithmetic Circuits
Chapter 5 (minus 5.3.4)
Positional Number Representation
• Decimal:
– D = dn-1dn-2...d1d0
– V(D) = dn-1  10n-1 + d n-2  10n-2 + ... + d1  101 + d0  100
• Binary:
– B = bn-1bn-2...b1b0
– V(B) = bn-1  2n-1 + b n-2  2n-2 + ... + b1  21 + b0  20 (5.1)
Conversion: Binary to/from Decimal
• Conversion of binary to decimal: use 5.1.
– (1101)2 =
• Conversion of decimal to binary:
–
–
–
–
–
–
V = bn-1  2n-1 + b n-2  2n-2 + ... + b1  21 + b0
V/2 = bn-1  2n-2 + b n-2  2n-3 + ... + b1 + b0/2
Quotient is: bn-1  2n-2 + b n-2  2n-3 + ... + b1
Remainder is: b0
If remainder is 0 then b0 = 0, if it is 1 then b0 = 1.
Repeat on quotient to find b1, etc.
Convert (857)10 to binary:
Figure 5.1
Conversion from decimal to binary
Table 5.1
Numbers in different systems
Conversion: Binary to Oct or Hex
• (101011010111)2
• (10111011)2
• (1010111100100101)2
• (1101101000)2
Addition of Unsigned Numbers
x
+y
---c s
carry
sum
Addition of Unsigned Numbers
x
y
c
s
(15)10
(10)10
Figure 5.3
An example of addition
Figure 5.4
Full-adder
Use of XOR Gates
Circuit for Full Adder
s
ci
s
xi
yi
HA
HA
c
si
ci + 1
c
(a) Block diagram
ci
si
xi
yi
ci + 1
(b) Detailed diagram
Figure 5.5
A decomposed implementation of the full-adder circuit
xn –1
cn
x1
yn – 1
FA
cn ”
1
sn – 1
c2
y1
x0
y0
c1
FA
FA
s1
s0
MSB position
LSB position
Figure 5.6
An n-bit ripple-carry adder
c0
x7
c7
x0
A : a7
a0
y7
y0
s7
s0
0
x8 x7
c8
P = 3A : P9
Figure5.7
x0
y8 y7
y0
s8
s0
P8
P0
(a) Naive approach
Circuit that multiplies an 8-bit unsigned number by 3
A : a7
0
x8
c8
P = 3A : P9
x1 x0
a0
0
y8 y7
y0
s8
s0
P8
P0
(b) Efficient design
Figure5.7
Circuit that multiplies an 8-bit unsigned number by 3
bn–1
b1
b0
Magnitude
MSB
(a) Unsigned number
bn–1 bn–2
Sign
0 denotes
+
–
1 denotes
b1
Magnitude
MSB
(b) Signed number
b0
Sign Magnitude
• Magnitude of positive and negative
numbers represented in same way.
• Sign used to distinguish them.
• Simple to understand.
• Complicates hardware design.
1’s Complement
• n-bit negative number found by subtracting
its positive form from 2n-1.
– K1 = (2n – 1) – P
• Found by just complementing each bit.
• Examples:
2’s Complement
• n-bit negative number found by subtracting
its positive form from 2n.
– K2 = 2n – P
– K2 = K1 + 1
• Complement each bit and add 1.
• Examples:
Sign Magnitude: Add/Sub
• If both operands have the same sign, then
addition is simple.
– Add magnitudes and copy the sign.
• If they have opposite sign, then must
subtract smaller from the larger.
• This is complicated, so sign magnitude not
typically used in computers.
(+ 5)
+ (+ 2)
(– 5 )
+ (+ 2)
(+ 7)
(- 3 )
(+ 5)
+ ( – 2)
(– 5 )
+ (– 2 )
(+ 3)
(– 7 )
Figure 5.9
Examples of 1’s complement addition
(+ 5)
+ (+ 2)
(– 5 )
+ (+ 2)
(+ 7)
(- 3 )
(+ 5)
+ ( – 2)
(– 5 )
+ (– 2 )
(+ 3)
(– 7 )
Figure 5.10
Examples of 2’s complement addition
(+ 5)
– (+ 2)
(+ 7)
(+ 5)
– ( – 2)
(+ 3)
Figure 5.11
Examples of 2’s complement subtraction
(– 5 )
– (+ 2 )
(- 3 )
(– 5 )
– (– 2 )
(– 7 )
Figure 5.11
Examples of 2’s complement subtraction
1111
1110
1101
1100
0000
–1 0
0001
0010
+1
–2
–3
+2
+3
–4
+4
–5
1011
–6
1010
1001
Figure 5.12
0011
0100
+5
–7 –8 +7
1000
+6
0101
0110
0111
Graphical interpretation of four-bit 2’s complement numbers
yn–1
xn–1
y1
y0
AddSub
control
x1 x0
cn
c0
n-bit adder
sn–1
s1
Figure 5.13
s0
Adder/subtractor unit
( + 7)
+ ( + 2)
(–7)
+ ( + 2)
( + 9)
(–5)
( + 7)
+ ( – 2)
(–7)
+ (–2)
( + 5)
(–9)
Figure 5.14
Examples of determination of overflow
Detecting Overflow
• Overflow = c3c4’ + c3’c4
= c3  c4
• For n-bit numbers,
• Overflow = cn-1  cn
Performance Issues
• Price/performance ratio is important.
• Speed of addition/subtraction has impact on
overall speed of a microprocessor.
• Worst-case delay of a ripple carry adder is:
–nt
– Assume  t = 2 gate delays and xor = 1.
– Total delay = 2n + 1 gate delays.
• Must reduce critical path delay.
Carry-Lookahead Adder
• Must determine carry quickly.
– ci+1 = xiyi + xici + yici
– ci+1 = xiyi + (xi + yi)ci
– ci+1 = gi+ pici where gi = xiyi
(generate)
pi = xi + yi (propagate)
– ci+1 = gi+ pi (gi-1+ pi-1ci-1)
– ci+1 = gi+ pigi-1+ pipi-1ci-1
– ci+1 = gi+ pigi-1+ pipi-1gi-2 + ...+ pipi-1...p1g0 +
pipi-1...p0c0
x1
g1
y1
x0
p1
g0
y0
p0
c1
c2
Stage 1
Stage 0
s1
Figure 5.15
c0
s0
A ripple-carry adder with generate/propagate signals
x1
y1
x0
x0
g1
p1
y0
y0
g0
p0
c0
c2
c1
s1
Figure 5.16
s0
The first two stages of a carry-lookahead adder
High Fan-in Issues
•
•
•
•
c1 = g0+ p0c0
c2 = g1+ p1g0+ p1p0c0
...
c8 = g7+ p7g6+ p7p6g5 + p7p6p5g4 + p7p6p5p4g3
+ p7p6p5p4p3g2 + p7p6p5p4p3p2g1
+ p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0
• c8 = (g7+ p7g6+ p7p6g5 + p7p6p5g4) + [(p7p6p5p4)(g3 +
p3g2 + p3p2g1 + p3p2p1g0) + (p7p6p5p4)(p3p2p1p0)c0
x15–8
x31–24 y31–24
c32
Block
3
s31–24
Figure 5.17
c24
c16
y15–8
Block
1
s15–8
x7–0 y7–0
c8
Block
0
c0
s7–0
A hierarchical carry-lookahead adder with ripple-carry between blocks
Group Propagate/Generate
• c8 = g7+ p7g6+ p7p6g5 + p7p6p5g4 + p7p6p5p4g3
+ p7p6p5p4p3g2 + p7p6p5p4p3p2g1
+ p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0
• P0 = p7p6p5p4p3p2p1p0
• G0 = g7+ p7g6+ ... + p7p6p5p4p3p2p1g0
• c8 = G0 + P0c0
• c16 = G1 + P1G0 + P1P0c0
• c24 = G2 + P2G1 + P2P1G0 + P2P1P0c0
• c32 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0
x31 – 24 y31 – 24
Block
3
x15 – 8
y15 – 8
x7 – 0
Block
1
c24
G3 P3
Block
0
G1 P1
s31 – 24
c32
G0 P0
s15 – 8
c16
s7 – 0
c8
Second-level lookahead
Figure 5.18
y7 – 0
A hierarchical carry-lookahead adder
c0
x1
g1
y1
x0
p1
g0
y0
p0
c0
c2
c1
s1
Figure 5.19
s0
An alternative design for a carry-lookahead adder
Figure 5.20
Schematic using an LPM adder/subtractor module
Optimized for cost
Optimized for speed
Figure 5.21
Simulation results for the LPM adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( Cin, x, y : IN
STD_LOGIC ;
s, Cout : OUT
STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
Figure 5.23
VHDL code for the full-adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY adder4 IS
PORT ( Cin
x3, x2, x1, x0
y3, y2, y1, y0
s3, s2, s1, s0
Cout
END adder4 ;
: IN
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c1, c2, c3 : STD_LOGIC ;
COMPONENT fulladd
PORT ( Cin, x, y : IN
STD_LOGIC ;
s, Cout
: OUT
STD_LOGIC ) ;
END COMPONENT ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
Figure 5.24
VHDL code for a four-bit adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE fulladd_package IS
COMPONENT fulladd
PORT ( Cin, x, y
: IN STD_LOGIC ;
s, Cout
: OUT STD_LOGIC ) ;
END COMPONENT ;
END fulladd_package ;
Figure 5.25
Declaration of a package
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin
x3, x2, x1, x0
y3, y2, y1, y0
s3, s2, s1, s0
Cout
END adder4 ;
: IN
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c1, c2, c3 : STD_LOGIC ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
Figure 5.26
Using a package for the four-bit adder
STD_LOGIC_VECTOR’s
• SIGNAL C : STD_LOGIC_VECTOR(1 TO 3);
• C <= “100” equivalent to:
– C(1) = ‘1’, C(2) = ‘0’, C(3) = ‘0’
• SIGNAL X : STD_LOGIC_VECTOR(3 DOWNTO 0);
• X <= “1100” equivalent to:
– X(3) = ‘1’, X(2) = ‘1’, X(1) = ‘0’, X(0) = ‘0’
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin
X, Y
S
Cout
END adder4 ;
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;
stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;
stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
END Structure ;
Figure 5.27
A four-bit adder defined using multibit signals
Arithmetic Packages
• std_logic_signed package defines signed
arithmetic for std_logic type.
• std_logic_unsigned package defines
unsigned arithmetic for std_logic type.
• These are built on top of the package
std_logic_arith.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY adder16 IS
PORT ( X, Y
S
END adder16 ;
: IN
: OUT
STD_LOGIC_VECTOR(15 DOWNTO 0) ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF adder16 IS
BEGIN
S <= X + Y ;
END Behavior ;
Figure 5.28
VHDL code for a 16-bit adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY adder16 IS
PORT ( Cin
X, Y
S
Cout, Overflow
END adder16 ;
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF adder16 IS
SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
Figure 5.29
A 16-bit adder with carry and overflow
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY adder16 IS
PORT ( Cin
X, Y
S
Cout, Overflow
END adder16 ;
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
SIGNED(15 DOWNTO 0) ;
SIGNED(15 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF adder16 IS
SIGNAL Sum : SIGNED(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
Figure 5.30
Use of the arithmetic package
ENTITY adder16 IS
PORT ( X, Y
S
END adder16 ;
: IN
: OUT
INTEGER RANGE -32768 TO 32767 ;
INTEGER RANGE -32768 TO 32767 ) ;
ARCHITECTURE Behavior OF adder16 IS
BEGIN
S <= X + Y ;
END Behavior ;
Figure 5.31
A 16-bit adder using INTEGER signals
Multiplication
• Binary number can be multiplied by 2
shifting it one position to the left:
– B = bn-1 bn-2 ... b1b0
– 2  B = bn-1 bn-2 ... b1b00
• Similarly, multiplying by 2k can be done by
shifting left by k bit positions.
• Right shifts divide by powers of 2.
Multiplicand M
Multiplier Q
(14)
(11)
(a) Multiplication by hand
Figure 5.32
Multiplication of unsigned numbers
1110
 1011
Multiplicand M
Multiplier Q
(11)
(14)
1110
 1011
Partial product 0
Partial product 1
Partial product 2
Product P
(b) Multiplication for implementation in hardware
Array Multiplier
• M = m3m2m1m0 and Q = q3q2q1q0
• Partial product 0:
– PP0 = m3q0 m2q0 m1q0 m0q0
• Partial product 1:
PP0:
0 pp03 pp02 pp01 pp00
+
m3q1 m2q1 m1q1 m0q0
0
--------------------------------------------------------PP1:
pp14 pp13 pp12 pp11 pp10
Figure 5.33
A 4 x 4 multiplier circuit
0
m3
m2
m1
m0
q0
0
PP1
q1
q2
0
PP2
q3
0
p7
p6
p5
p4
p3
p2
p1
p0
(a) Structure of the circuit
mk + 1
mk
Bit of PPi
mk
q0
q1
c out
FA
(b) A block in the top row
c in
qj
c out
FA
(c) A block in the bottom two rows
c in
Multiplicand M
Multiplier Q
(+14)
(+11)
Partial product 0
Partial product 1
Partial product 2
Partial product 3
Product P
(+154)
(a) Positive multiplicand
01110
x 01011
Multiplicand M
Multiplier Q
(–14)
(+11)
Partial product 0
Partial product 1
Partial product 2
Partial product 3
Product P
(–154)
(a) Negative multiplicand
10010
x 01011
Fixed-Point Numbers
• A fixed-point number consists of an integer
and fraction part.
– B = bn-1bn-2...b1b0 . b-1b-2...b-k
– V(B) =
• The position of the radix point is fixed.
• Circuits for fixed point same as integer.
Floating-Point Numbers
• Fixed-point numbers range limited by the
number of significant digits.
• Floating-point numbers needed to represent
very large or very small numbers.
– Mantissa  RExponent
• Numbers are normalized such that radix
point placed to right of first nonzero digit.
32 bits
S
Sign
+
0 denotes
–
1 denotes
E
8-bit
excess-127
exponent
M
23 bits of mantissa
(a) Single precision
64 bits
S
Sign
M
E
11-bit excess-1023
exponent
52 bits of mantissa
(c) Double precision
Figure 5.35
IEEE standard floating-point formats
Table 5.3
Binary-coded decimal digits
X
+ Y
Z
carry
0111
+ 0101
7
+ 5
1100
+ 0110
12
10010
S=2
X
+ Y
1000
+ 1001
8
+ 9
Z
10001
+ 0110
17
carry
10111
S=7
Figure 5.36
Addition of BCD digits
BCD Addition
• Z=X+Y
• If Z <= 9 then S = Z and carry-out = 0
• If Z > 9 then S = Z + 6 and carry-out = 1
X
Y
c in
4-bit adder
carry-out
Z
Detect if
sum 9
>
6
Adjust
c out
0
MUX
4-bit adder
0
S
Figure 5.37
Block diagram for a one-digit BCD adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY BCD IS
PORT ( X, Y
S
END BCD ;
: IN
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF BCD IS
SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ;
SIGNAL Adjust : STD_LOGIC ;
BEGIN
Z <= ('0' & X) + Y ;
Adjust <= '1' WHEN Z > 9 ELSE '0' ;
S <= Z WHEN (Adjust = '0') ELSE Z + 6 ;
END Behavior ;
Figure 5.38
VHDL code for a one-digit BCD adder
Figure 5.39
Functional simulation of the one-digit BCD adder
x3 x2 x1 x0
y3 y2 y1 y0
cin
Four-bit adder
z3
z2
z1
z0
Two-bit adder
cout
s3
Figure 5.40
s2
s1
s0
Circuit for a one-digit BCD adder
Table 5.4
The seven-bit ASCII code
Parity
• Parity widely used for error-checking.
• Data transmitted over long wires may be corrupted
during transit.
• Extra parity bit p is added to detect an error.
• Even parity: p set to make number of 1’s even.
– p = x3  x2  x1  x0
– c = p  x3  x2  x1  x0
• Odd parity: p set to make number of 1’s odd.
Summary
•
•
•
•
•
•
Positional number representation.
Addition of unsigned/signed numbers.
Carry-Lookahead adder.
Arithmetic circuit design using VHDL.
Multiplication.
Other number representations.