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Outline
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Introduction – “Is there a limit?”
Transistors – “CMOS building blocks”
Parasitics I – “The [un]desirables”
Parasitics II – “Building a full MOS model”
The CMOS inverter – “A masterpiece”
Technology scaling – “Smaller, Faster and Cooler”
Technology – “Building an inverter”
Gates I – “Just like LEGO”
The pass gate – “An useful complement”
Gates II – “A portfolio”
Sequential circuits – “Time also counts!”
DLLs and PLLs – “ A brief introduction”
Storage elements – “A bit in memory”
Paulo Moreira
Transistors
1
“CMOS building blocks”
• “Making Logic”
• Silicon switches:
– The NMOS
– Its mirror image, the PMOS
• Electrical behavior:
– Strong inversion
• Model
• How good is the approximation?
– Weak inversion
– Gain and inversion
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“Making Logic”
• Logic circuit “ingredients”:
–
–
–
–
Power source
Switches
Power gain
Inversion
• Power always comes from
some form of external EMF
generator.
• NMOS and PMOS
transistors:
– Can perform the last three
functions
– They are the building blocks
of CMOS technologies!
Paulo Moreira
Transistors
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Silicon switches: the NMOS
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Transistors
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Silicon switches: the NMOS
Above silicon:
• Thin oxide (SiO2) under the gate areas;
• Thick oxide everywhere else;
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Transistors
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Silicon switches: the PMOS
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MOSFET equations
• Cut-off region
• Linear region
I ds  0
for
Vgs  VT  0
2

V 
I ds    Cox    Vgs  VT  Vds  ds   1    Vds  for 0  Vds  Vgs  VT
L 
2 


W

• Saturation
I ds 

  Cox W
2

L

 Vgs  VT

2
 1    Vds  for Vds  Vgs  VT
• Oxide capacitance

Cox  ox
t ox
 F / m2 
0.24m process
• Process “transconductance”
  Cox 
Paulo Moreira
  ox
t ox
A / V 
2
Transistors
tox = 5nm (~10 atomic layers)
Cox = 5.6fF/m2
7
MOS output characteristics
• Linear region:
Vds<Vgs-VT
– Voltage controlled
resistor
• Saturation region:
Vds>Vgs-VT
– Voltage controlled
current source
• Curves deviate from the
ideal current source
behavior due to:
– Channel modulation
effects
Paulo Moreira
Transistors
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MOS output characteristics
L = 240nm, W = 480nm
250
Vgs = 0.7V (< Vt)
Vgs = 1.3V
Vgs = 1.9V
Vgs = 2.5V
Ids [uA]
200
150
100
50
0
0
0.5
1
1.5
2
2.5
Vds [V]
Paulo Moreira
Transistors
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MOS output characteristics
L = 24um, W = 48um
400
Vgs = 0.7V (<Vt)
Vgs = 1.3V
Vgs = 1.9V
Vgs = 2.5V
350
Ids [uA]
300
250
200
150
100
50
0
0
0.5
1
1.5
2
2.5
Vds [V]
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Bulk effect
• The threshold depends on:
V=VT0
V=0
– Gate oxide thickness
– Doping levels
– Source-to-bulk voltage
• When the semiconductor
surface inverts to n-type
the channel is in “strong
inversion”
• Vsb = 0  strong inversion
for:
p+
n+
n+
V>VT0
V>0
– surface potential > -2F
• Vsb > 0  strong inversion
for:
p+
n+
n+
– surface potential > -2F + Vsb
Paulo Moreira
Transistors
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Bulk effect
600
W = 24m
L =L =48m
24um, W = 48um, Vbs = 1
500
Vsb = 0V
L = 24um, W = 48um, Vbs = -1V
Vsb = 1 V
Ids [uA]
400
300
200
100
0
0
0.5
1
1.5
2
2.5
Vgs [V]
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Transistors
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Mobility
  Cox 
  ox
t ox

A/V
2

The current driving capability
can be improved by using materials
with higher electron mobility
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Transistors
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Is the quadratic law valid?
Ids - Vgs (Vds = 2.5V, Vbs = 0V)
600
L = 24um, W = 48um
500
Quadratic “law” valid for
long channel devices only!
L = 2.4um, W = 4.8um
L = 240nm, W = 480nm
Ids [uA]
400
300
200
100
0
0
0.5
1
1.5
2
2.5
Vgs [V]
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Weak inversion
• Is Id=0 when Vgs<VT?
• For Vgs<VT the drain current
depends exponentially on
Vgs
• In weak inversion and
saturation (Vds > ~150mV):
qVgs
Id 
W
 I do  e nk T
L
where
I do  e

q VT
nk T
• Used in very low power
designs
• Slow operation
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Transistors
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Gain & Inversion
• Gain:
– Signal regeneration at
every logic operation
– “Static” flip-flops
– “Static” RW memory cells
• Inversion:
– Intrinsic to the commonsource configuration
• The gain cell load can
be:
– Resistor
– Current source
– Another gain device
(PMOS)
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