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PACS IBDR
27/28 Feb 2002
PACS IBDR
Warm Electronics,
Grounding and EMC
Martin von Berg
Warm Electronics
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PACS IBDR
27/28 Feb 2002
Warm Electronics Overview
Warm Electronics
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PACS IBDR
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Warm Electronics Development
• BOLA
– Mechanical design updated
– Box thermal behavior modeling in progress
– JFET modeling for effect of temperature on performance in
progress
• BOLC
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Mechanical design BOLC updated (2 stacked boxes)
Analogue board prototype ready for performance test
Bolometer bias board (QM1) ready for design
“300mK” temperature control prototype designed
FPGA implementation of IEEE1355 under test at CSL
Most digital functions designed, except bolometer sequencer
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PACS IBDR
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Warm Electronics Development
• DEC/MEC
– DEC/MEC AVM Status
• DSP and DEC simulator available / development on schedule
– DEC/MEC EM Status
• design and procurement ongoing, but validation with representative
hardware pending on mechanism simulators availability from partners
– DEC/MEC On-board Software Status
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sequencer complete
communication 70% tested
mechanism control low-level S/W ~ 0%
MEC-to-DPU simulator completed: Virtuoso + OBS emulated on a PC
– Successful operation of CRE with DEC prototype
• low noise + good linearity
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PACS IBDR
27/28 Feb 2002
Grounding Concept
S/C-Bus
Warm Electronics
Instr.-Bus
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PACS IBDR
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Grounding Concept
• Distributed Star Ground
 SVM Panel is S/C GND (Chassis)
 Housings to S/C GND
 Internal GND flexible on S/C GND
 Overshields on S/C GND via Backshells 360°
 Symmetric lines ar far as possible
 Galvanic Decoupling
 Shields to internal GND on driven side
 Document PACS-ME-LI-006
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PACS IBDR
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EMC Design
 Analysis by T. Bax
 PSpice Simulation by T. Bax
 Cryo Harness definition
 Information Flux Problem
Transfer impedance, Microphonic Noise
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Open topics:
 Connection from CVV to SVM
 Calculation of ESD-Sensitivity
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PACS IBDR
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EMC Tests
• Units
– Complete Tests
• AVM
– MPE: Conducted Susceptibility Common Mode
– T. E. is in preparation
• EQM
– Complete Testing according to IID-B
– Two instrument modes:
• PACS most sensitive
• PACS most disturbing
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PACS IBDR
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Other Aspects
• Mechanical I/F to SVM
 Dimensions of BOLC and DECMEC
 Connector positions
 Mass of BOLC and DECMEC
• Distribution Board fixed but
missing Resistor values
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PACS IBDR
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SVM Panel Accomodation
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SVM Panel Dimensions: 1114.5 x 796.5 mm²
S/C Constraints reduce available area:
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Side: 85 mm, Bottom: 50 mm, Top: 95 mm variable (Box Height)
Additional Space for S/C Conn. Bracket: 150x250mm² (# of Conn)
Space between Boxes: 30 mm; All Data TBC by Alenia
Box-Dimensions:
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BOLC: 499.5 x 289 x 376.9 mm³ incl. Connector backshell dim.
DECMEC: 582 x 318 x 300 mm³ including feet
DPU: 274 x 258 x 194 mm³ including feet
SPU: 270 x 258 x 102 mm³ including feet
 Inconsistence: assumed Space <=> Box Dimensions
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PACS IBDR
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SVM Panel Accomodation
• Proposal:
1. Stack the two SPUs
2. Reduce Length of DECMEC to less than 560 mm
3. Move lateral BOLC Connectors
 Accomodation and Harness routing is possible
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