Download Lec #2, CMOS Logic Circuits.

Goal of this lecture
Present understanding of device operation
 nMOS/pMOS as switches
 How to design complex gates using
nMOS/pMOS transistors

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What is a Transistor?
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
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The MOS Transistor
Polysilicon
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Aluminum
3
Devices
CMOS devices
NMOS
PMOS
Polysilicon
Al
Gate
SiO2
Gate
W
L
p+
n+
n+
p+
Source
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n+
n-well
p-substrate
Substrate
contact
p+
Drain
Drain
Source
n-well
contact
4
Devices
The NMOS





Substrate: lightly doped (p-)
Source and drain: heavily doped (n+)
Gate: polysilicon
Thin oxide separates the gate and the “channel”
Field oxide and field implant isolate the devices
NMOS Transistor
Polysilicon
Gate
Field oxide
(SiO2)
Drain
Source
n+
n+
p-substrate
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Gate oxide
p+ field implant
5
Devices
MOS Transistors Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
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D
B
S
NMOS with
Bulk Contact
6
Devices
Threshold Voltage: Concept
+
S
VGS
-
D
G
n+
n+
Depletion
Region
n-channel
p-substrate
B
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Devices
Transistor in Linear
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
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Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
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Summary of MOSFET Operating
Regions
 Strong
Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak
Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence
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MOSFET equations


Cut-off region
I ds  0
Linear region
for
Vgs  VT  0
2

V 
I ds    Cox    Vgs  VT  Vds  ds   1    Vds  for 0  Vds  Vgs  VT
L 
2 


W


Saturation
I ds 


  Cox W

2
L

 Vgs  VT

2
 1    Vds  for Vds  Vgs  VT
Oxide capacitance/Gain Factor

Cox  ox
t ox
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
F/m
2


  t ox W/L
ox
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Mobility
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ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
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2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
Short Channel
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Devices
MOS output characteristics



Linear region: Vds<Vgs-VT
 Voltage controlled
resistor
Saturation region: Vds>Vgs-VT
 Voltage controlled current
source
Curves deviate from the
ideal current source behavior
due to:
 Channel modulation
effects
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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Static Complementary CMOS
VDD
In1
In2
PUN
InN
In1
In2
InN
PMOS only
F(In1,In2,…InN)
PDN
NMOS only
PUN and PDN are dual logic networks
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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
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Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
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CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
CL
D
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Complementary CMOS Logic Style
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Example Gate: NAND
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Example Gate: NOR
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Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
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C
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Devices
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
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Cell Design
 Standard
Cells
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath
Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width
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Standard Cells
N Well
VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
In
2
Cell boundary
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Out
GND
Rails ~10
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Devices
Standard Cells
With minimal
diffusion
routing
VDD
With silicided
diffusion
VDD
VDD
M2
In
Out
In
Out
In
Out
M1
GND
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GND
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Devices
Standard Cells
VDD
2-input NAND gate
VDD
B
A
B
Out
A
GND
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