Download EE372 VLSI SYSTEM DESIGN E. Yoon

EE372 VLSI SYSTEM DESIGN
E. Yoon
Latch-up & Power Consumption
Latch-up Problem
Vdd
I2 
Rsub
2
1
I1 
GND
Integrated Microsystems Lab.
Rw
VW
Latch-up condition
1 2 >1
11-1
EE372 VLSI SYSTEM DESIGN
VW  V o n ~ 0 .6 V
1 
E. Yoon

 V s  1  R sub 
 2 
 Vw 
I
Vdd-GND
VL
Integrated Microsystems Lab.
(I/o drive /pads)
11-2
EE372 VLSI SYSTEM DESIGN
E. Yoon
Latch-up Solutions
1) Reduce 
RW , Rsub
2) Many contacts to substrate and well
3) Guard rings for transistors with W > 100m
Vdd
GND
PMOS
NMOS
P+
Brown
4) Epi -layer
5) SOI
Integrated Microsystems Lab.
N+
Green
11-3
EE372 VLSI SYSTEM DESIGN
E. Yoon
CMOS Latch-up and It’s Preventions
 What is CMOS Latch-up?
— CMOS latch-up is a parasitic circuit effect in which both npn and
pnp transistors are turned on at the same time. The result of this
effect is the shortening of the VDD and VSS lines. Current no
longer flows thru the surface channel, but thru the bulk and the
junctions, the signal outputs will be latched at an unknown state
(0.85~1.5V).
— IDD current will increase until they self-limit or until they result
in the destruction of the chip or it’s bonding leads.
— Once it is being latched, the only way to restore it’s function is to
turn off/on the power.
For example: n-well CMOS epi technology
Integrated Microsystems Lab.
11-4
EE372 VLSI SYSTEM DESIGN
E. Yoon
npn=0.5~10 depends on the distance between n+ to n-well
pnp =50~100 depends on the base width (XJN-well—XJP+)
RW =1k~20k depends on N-well sheet resistance and distance between
n+and P+
RS =10(for p- / p+ epi) 500-700 for bulk substrate
Integrated Microsystems Lab.
11-5
EE372 VLSI SYSTEM DESIGN
E. Yoon
How to prevent latch-up?
— Reduce current gain of parasitic bipolar transistor
 npn  pnp >1 by suitable vertical process design and
horizontal spacings. But for high packing density VLSI, this
is difficult to achieve.
— Reduce Rs and Rw
Rw, by putting more n-well plugs (VDD) or sorrunding
n-well with n+ guard rings.
Rs, by putting more p+ plugs (ground) in substrate, or with
p- /p+ epitaxial layer substrate.
— Put top side ring as surface ground contact or use backside
contact as ground.
— Use trench isolation or silicon on Sapphare Sustrate.
— If use epi, n+ —p+ spacing should be greater than the epitaxial
thickness.
— Special attention on the I / O pad, put guard rings around the
buffer circuit.
Integrated Microsystems Lab.
11-6
EE372 VLSI SYSTEM DESIGN
E. Yoon
ESD (Electrostatic Discharge)
concerns in Input Protection Circuit
Human body model
Typical input protection circuit
1.5k
2000V
1000pF
VDD
1~2k
Finger tip
Total energy stored
1/2CV2=0.210-3 J
pad
Two mechanisms in ESD effect.
1. Oxide rupture
2. Poly Si resistor, or pn junction burned out.
Integrated Microsystems Lab.
VDD
11-7
EE372 VLSI SYSTEM DESIGN
E. Yoon
SiO2 dielectric strength 6106V/cm
(thinner oxide, the dielectric strength
even higher)
if 650Å, BV=39V
if 300Å, BV=25V
SiO2
Si
The voltage that can build up on a gate may be determined from
V 
t
Cg
If charging current 10A, charging time 1s, Cg=0.03pF,
then V=330V !!! It will definitely rupture gate oxide.
Conventionally, use two clamping diodes plus one resistor (1~2K), this
resistor is for current limiting purpose, preferably using poly silicon
line, but the strength of poly is not as good as that of a diffusion resistor.
In high speed circuit, one should watch out the extra RC delay due
to current limiting resistor. The area of clamping diodes will determine
power dissipation capability.
Integrated Microsystems Lab.
11-8
EE372 VLSI SYSTEM DESIGN
E. Yoon
11-9
Some Layout Precautions on latch-up
1. Separate PMOS. NMOS driver transistors
2. P+ guard rings around NMOS and connected to VSS
3. N+ guard rings around PMOS and connected to VDD
VDD
P+ VSS
N+
NMOS
PAD
PMOS
4. Employ minimum area P-well, minimize photo current during transistor.
5. Source fingers of PMOS / NMOS prefer to be perpendicular to the
current flow direction
PMOS

Current direction

Integrated Microsystems Lab.
NMOS
EE372 VLSI SYSTEM DESIGN
E. Yoon
6. P-well should hard wired to GND, N-sub should hard wired to VDD,
VDD, VSS face each other.
n+
P+n
P+n+P+n+P+
+
tied to VDD by metal from VDD
line, not just got VDD from
substrate.
P-well
tied to GND by metal running over
7. Spacing between p+ and n+ (in p-well) should be minimum (“d” can
be zero.) Spacing between n-sub n+ and p+ source should be minimum.
d
d
p+
n+
p+
n+
n+
P-
nIntegrated Microsystems Lab.
p+
11-10
EE372 VLSI SYSTEM DESIGN
E. Yoon
Potential Well/Sub Contact Problem
Signal
p+
GND
n+
n+
D
Misplaced
Substrate
Contact
p-sub
S
Signal (Drain)
p+/p-sub
n+(source)
Integrated Microsystems Lab.
p+
11-11
EE372 VLSI SYSTEM DESIGN
E. Yoon
11-12
Floating Well Pass Transistor (DON’T FORGET WELL TABS!)
CLK
in
out
p+
D
p+
n-well
S
CLK
in
Vdd
Integrated Microsystems Lab.
IN
0
1
VG
Vwell
out
1(off)
u
0(on)
VX
(VDD - VD,on)
1(off)
VX
0
0(on)
VX
0
1(off)
VX
01 1(off)
VX
Vout
0
1
1
0
0
1
EE372 VLSI SYSTEM DESIGN
E. Yoon
Power Consumption For CMOS
(1) Static dissipation
If there is no pseudo NMOS pull-rp or other resistive current
path, the only static power dissipation is from junction leakage.
n
S tatic P o w er   leakag e curren ts  S up p le V o ltag e
1~ 2 n ean o w atts /in verter
A useful estimate is to allow a leakage current of 0.1nA to 0.5nA
per gate at room temperature.
 Junction Leakage
<Example> 106 gate circuits
Itotal = 0.5nA 106 =0.5mA
Power = Itotal 5V=2.5mW
 Gate Leakage
(10pA/m)  (10m)  10M ~1mA
Power = 1mA  5V= 5mW
Integrated Microsystems Lab.
11-13
EE372 VLSI SYSTEM DESIGN
E. Yoon
Power Consumption in CMOS (cont’d)
(2) Dynamic Power
R
R
Energy  Power  time

   power   dt   i t   R  dt
2
0
i t  


V
exp t / RC
R

V2
Energy 
exp  2t / RC  dt

R 0
V 2 C
0  1  1 CV 2 Joules

2
2
2
AVGPower  CV  f Joules / sec Watts
For entire chip P  F  CV 2  f (where F is fraction of switching)
Integrated Microsystems Lab.
11-14
EE372 VLSI SYSTEM DESIGN
E. Yoon
Dynamic dissipation (cont’d)
(a) Switching transient current Psw (small)
VDD
VDD - | Vtp |
Vtn
t
Isw
t1 t2 t3
t
Psw   mean  VDD
t2
 1 t3

2 
2
 mean  2    t dt   2   Vin t   Vt  dt
T
T
2
t1
 t1

V
t
tr
whareVin t   VDD  ,t1  t tr,t 2 
tr
VDD
2
Psw 

12
VDD  2Vt 3 tr
T
 Slow rising/falling results in power dissipation
of noise susceptibility (Psw  as tr )
Integrated Microsystems Lab.
11-15
EE372 VLSI SYSTEM DESIGN
E. Yoon
Dynamic dissipation (cont’d)
(b) Charging and discharging of load capacitance (dominant)
Pd  CL V 2 DD  fp
V  0  C V 2 f 
dV

 VDDCL DD
DD 
 P  VDD  VDDCL
L
dt

t


Ex:
1MG  60 fF
4MG  ~ 240 fF
P  60 fF 3.3 100MHz 1M gates
 60W
2
If the chip function consists of several frequencies, then the total
power consumption will be:
P d to tal  C L 1  fp 1  C L 2  fp 2  C L 3  fp 3   V
2
DD
Note: the power dissipation is independent of the device parameters
Integrated Microsystems Lab.
11-16
EE372 VLSI SYSTEM DESIGN
E. Yoon
Power consumption For NMOS
For NMOS inverter, assume 50% duty cycle


P d  D D VO L   D D VO H  V D D
1
2
1

2


0  D ,sat V D d
2

V
 2 TD V D d


2
1W L 
 nC o x VTD V D D 

4 LL 
For minimum power
WL=Wmin, LL=kRLmin
Integrated Microsystems Lab.
11-17