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PADFRAME
Michael Karagounis
Questions & Answers LVDS 1
Question: Do your LVDS circuits meet the specs of the LVDS standard
Answer: No, but they are compatible to commercial LVDS circuits
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
LVDS Driver Restrictions
• Only Thin-Gates Transistors -> max. voltage 1.2-1.5V
Vbp
• Maximum output voltage before current source leaves
saturation  VDD- 250mV
5pF
D
D
M3
• LVDS standard defines a common mode range of 0 – 2.4V
for the LVDS receiver
M4
TX A commercial LVDS receiver (e.g. FPGA input) is able to
process the data signal
CMOS
driver
CMFB
100k
Vcm
100k
Vofs
D
M5
5pF
03.11.2009
M6
TX
Vbn
FE-I4 Review - Padframe - Michael Karagounis
Slide 3
LVDS Receiver Restrictions
Rail-to-Rail Input stage
 max. input voltage limited by VDD
M11 M12
M9
M13 M14
M15
M10
M17
M14
Option2:
M18
OUT
IN2
 Override Driver Common Mode Voltage
I out
M1
M2
Option1:
To process standard LVDS signal 1.2V +/- 175mV
VDD >= 1.375 V
M8
IN1
M16
M19
M20
+
M3
TX
-
M4 M5
+
M6 M7
M21
RX
-
M22
Option 3:
Tyhach et al., A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data
Rate for Source-Synchronous System and 300-MHz Clock
Rate for External Memory Interface, IEEE JSSC, Sept. 2005
03.11.2009
Use LVDS transceiver chip in test setup
FE-I4 Review - Padframe - Michael Karagounis
Slide 4
Questions & Answers LVDS 2
Question: Does your receiver reach an intermediate state of high current
consumption? ( Is your receiver Fail-Safe?)
Answer: No, because we bias the receiver input (Yes it is Fail-Safe)
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Failsafe-Biasing
• bias voltage close to VDD/2 is defined by resistive divider
• bias is fed to RX inputs by high ohmic resistors
• additional high ohmic resistor connected between inverted
input & ground introduces voltage difference @ inputs
+
RX
60mV
-
Maxim Application Note 4007,
Robust Fail-Safe Biasing for AC-Coupeled Multidrop LVDS Bus, 2007
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
AC Coupled Communication Scheme
TX
On-Chip
RX
I out
+
+
TX
-
RX
-
approach allows to study AC-coupled communications scheme
 DC – Balancing can be achieved by sending commands with wrong chip id
& complementary data during command data transmission breaks
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
CMOS
OUT
Self-Biasing of LVDS Receiver
START-UP
Vbias
consequence of power-on sequence:
LVDS receiver has to be fully functional before the precise
reference circuit is available
 LVDS receiver has to be self biased
R1
R2
R3
LVDS receiver biasing has to be reliable
• modified version of low voltage beta-multiplier (M1, R2 & R3 have been added)
(Baker, CMOS, 2nd edition, IEEE press p. 629)
• reference current is defined by R1 (R1=R2=R3)
• circuit has only one dominant pole  easy to compensate
• addition of transistor M1 gives first order temperature compensation
(Friori, A New Compact Temperature compensated CMOS current reference, IEEE Trans. Circ. & Sys., 2005)
• start-up circuit enforces current flow in the circuit and switches off during normal operation
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Reference Current vs. Supply Voltage
reference current stays stable for VDD > 1.0
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Reference Current vs. Temperature
variation of referene current < 300nA with temperature
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Monte Carlo Simulation
Imean=23.7 uA, Isigma=1.3 uA, Imin=17.5uA,Imax=32.5uA
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Monte Carlo: RiseTime & Duty Cycle
Rise Time
Duty Cycle
Mean:217ps
Sigma:20ps
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Mean:50.4%
Sigma:0.5%
Slide 12
STATUS: LVDS circuits
• Layouts have been adapted to the longer bondpad pitch of
production chip (with respect to the test chips)
 LVDS driver has now more width & less height
OLD
• Metalization has been changed from LM to DM
• Design has been ported fom Tripple-Well to T3 substrate
isolation option
NEW
• LVDS biasing & failsafe circuits designed & layouted
Extraction & simulations of parasitics has not been done yet
LVDS driver
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Pad Frame
20mm
L
D
O
VDDA1
A
0
10
20
30
L
D
O
VDDD1
40
VDDA2
50
60
70
VDDD2
80
90
DC
DC
D
100
110
120
00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99
LL
D
D
O
O
A
A
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
P
P
R
R
O
O
B
B
E
E
LL
D
D
O
O
A
A
II
N
N
LL
D
D
O
O
A
A
O
O
U
U
TT
LL V
V
D
DR
R
O
OE
E
A
A FF
G
GO
O
N
NV
V
D
DE
E
R
R
R
R
II
D
D
E
E
50 Power
22 Digital I/O
13 Analog I/O
21 Probe
128 Overall
133 Maximum
55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66 77 88 99 00 11 22 33 44 55 66
D
D
C
C
D
D
C
C
LL
D
D
O
O
D
D
V
V
LL
R
R
D
D
E
E
O
O
FF
G
G
O
O
N
N
V
V
D
D
E
E
R
R
R
R
II
D
D
E
E
LL
D
D
O
O
D
D
O
O
U
U
TT
O
O
U
U
TT
&
&
LL
D
D
O
O
D
D
II
N
N
D
D
C
C
D
D
C
C
II
N
N
D
D
C
C
D
D
C
C
C
C
A
A
P
P
TT
O
O
P
P
D
D
C
C
D
D
C
C
D
D
C
C
D
D
C
C
C
C
C
C LL PP PP PP PP PP PP PP PP PP PP
A
A KK RR RR RR RR RR RR RR RR RR RR
O
P
OO
OO
OO
OO
OO
OO
OO
OO
OO
O
P
B
B
O
O
TT
TT
O
O
M
M
O
OB
B B
B B
B B
B B
B B
B B
B B
B B
B B
B
V
V E
E E
E E
E E
E E
E E
E E
E E
E E
E E
E
E
E
R
R
R
R
II
D
D
E
E
GND
VDDA
VDDD
DCDC-OUT
External power routing  Possibility to study different powering schemes
Pads grouped together to independent supply domains
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
OFF - CHIP
Bond Pads
INPUT
PAD
CORE
VDD
GND
SUB
VDDT3
OUTPUT
PAD
CORE
POWER
PAD
CDM diodes
M3/MQ/MG
M3/MQ/MG
M3/MQ/MG
M3/MQ/MG
200 um
HBM diodes
HBM diodes
100um
RC-Clamp
250 um
300 um
150 um
• 150um bond pitch
• Two different bond pad sizes
 100um x 200um I/O pads
 250um x 200um power pads (corresponds to two I/O pads)
• ESD devices, vertical M2 & horizontal M3,MQ,MG supply rail routing below the pad
• Only supply voltage & ground of according supply domain is routed below the pads
• VDDT3 rail is either connected to dedicated pad (digital domain) or shorted to VDD
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Bond Pad Layout
Spacer
Cell
Cut
Cell
ESD
• ESD devices are located in upper part of
the pad
• lower part has been kept empty for TSV
• Spacer cells are placed between the pads
• cut cells seperare pads of different
supply domains & provide bus to bus ESD
protection
120um empty
for TSV tests
Analog
Input
Pad
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Question & Answer ESD
Question: Do you follow a dedicated ESD strategy?
Answer: Yes, we follow the recommendation of the IBM ESD manual!
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
ESD strategy
Ground-to-Supply Discharge
VDDT3
VDDA
VDDD
GNDA
GNDD
SUB
Bus-to-Bus Protection
Output Pad
RC-Clamp
• I/O pads are connected via reverse-biased diodes to the supply rails
• Inputs have seconde diode pair & series resistor
 limit max. voltage @ gate of transistor
• Reverse biased diodes between VDD & GND rails
 discharge path from GND to VDD
• RC-Clamp shorts VDD & GND in case of positive going ESD event
 discharge path from VDD to GND
• Ground busses are protected by antiparallel diodes
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Input Pad
Status Padframe
All needed pad types have been developed:
Supply:
Digital:
Analog:
Analog VDD
CMOS IN
Analog IN
Digital VDD
CMOS OUT
Analog OUT
VDD 3.3V
LVDS IN
Wide Analog OUT
Wide VDD
LVDS OUT
GND
Wide GND
Substrate
VDDT3
Construction of pad frame ongoing
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
OLD & BACKUP SLIDES
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
LVDS Chip Submissions
• 21-Jul-2007: first test chip submitted to UMC 130nm via Europractice mini-asic run
 real hardware test of chosen architecture for use in FE-I4
• 24-Mar-2008: 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) via CERN
 for use in a SEU test setup
 characterization of new cables and flex types
• 15-Sep-2008: LVDS driver with tristate option submitted to IBM130nm (DM) via MOSIS
IBM 130nm (LM)
IBM 130nm (DM)
2mm
vrefLDO
gndLDO
gndLDO
gndLDO
gndLDO
vddIn
vddIn
vddIn
IoutDACn
vddIn
vddDAC
IoutDAC
gndSub
gndDAC
IbnDAC
DO
2 mm
1.8mm
IbpDAC
UMC 130nm
LD
DI
CLK
IbnLDO
vddOut
vddOut
vddOut
LDO
GNDD
VDDD
vddOut
gndSub
1.5mm
gndSub
IbnShuldoL
IbnShuldoR
VrefShuldoL
VrefShuldoR
2 mm
IinShuldo
IinShuldo
10 BIT DAC
IinShuldo
IinShuldo
IinShuldo
SHUNT
LDO
R
SHUNT
LDO
L
IinShuldo
IoutShuldo
IinShuldo
IinShuldo
IoutShuldo
IoutShuldo
IoutShuldo
IoutShuldo
2mm
IoutShuldo
IoutShuldo
Tristate
LVDS
IoutShuldo
RrefShuldoL
RrefShuldoR
100 um
VoutShuldoR
IrefShuldoR
VoutShuldoR
VoutShuldoR
TxLVDS
VoutShuldoR
TxnLVDS
IrefLVDS
VosLVDS
vddLvds
gndLvds
gndSub
VoutShuldoL
FE-I4 Review - Padframe - Michael Karagounis
VoutShuldoL
03.11.2009
VoutShuldoL
0.8mm
VoutShuldoL
IrefShuldoL
1.5mm
162.5 um
Slide 21
LVDS Transceiver-Chip Test Setup
Type 0 Cable Adapter
Type 0 Cable Adapter
Biasing
developed by A. Eyring
• 4 x LVDS receiver  CMOS output & CMOS input  LVDS driver
• Configurable Chain: LVDS receiver  LVDS driver
• 2x Type 0 cable adapter: LVDS signal  Type 0 cable  termination resistor  LVDS receiver
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
Measurements LVDS Transceiver Chip
Measurement with active differential probe and 100 Ohm termination resistor on PCB @ 1.2V supply
LVDS Rx In  LVDS Tx Out
@ 320 MHz Clock
LVDS RX In  CMOS Out
CMOS In  LVDS TX Out
Clock-Rate
Clock-Rate
320MHz
320MHz
160MHz
Input Common Mode Voltage
1.05V
600mV
160MHz
150mV
40MHz
40MHz
Increased biased currents needed for LVDS RX to operate
@ high frequences & low common mode voltages
measured by L. Gonella
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
LVDS Transceiver-Chip Eye Diagram
•
•
•
•
Test-Setup includes:
One – 4 meter twisted pair 36 AWG wire
(0.127 mm copper diameter)
160 Mbps data rate
Eye pattern is 317mV, need > 200mV
No errors @ 150 Mbps or 350 MbpsError rate better
than 2*10-13 @ 350 Mbps
IBL DATA TRANSMISSION TEST SETUP
XILINX DEVELOPMENT
BOARD - ML405
TEST CHIP LVDS DRIVER
50 CM PPA-0 FLEX
100 OHM
CMOS
DRIVER
50 OHM
HRS DF30
CONNECTOR
LVDS RECEIVER
100 OHM
350Mbps without cable
4 METER TWISTED PAIR 36-AWG
COPPER
80 OHM
160Mbps with cable
M. Kocian, D. Nelson, Su Dong SLAC
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
CMOS Input & Output Buffers
Input Buffer
M1
Vin
Output Buffer
M7
M5
M7
M2
Vout
M3
M4
Vin
M8
M1
M3
M5
M8
Vout
M2
M6
M4
M6
M9
M10
Schmitt-Trigger with 200mV hysteresis
• Cascoded structures have higher snapback voltage
• Have been used in LVDS-Transceiver chip
03.11.2009
FE-I4 Review - Padframe - Michael Karagounis
developed by D. Gnani