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PLC front-end Design Review
Curtis Mayberry
7-5-11
Revised Project Description
Block Diagram
RTD
TC
Thermistor
+/-10v, +/-5v
4-20mA
Signal
Conditioning
Stage 2
Stage 1
Cost-Effective
ADC
High-Accuracy
Super-Mini Dig
Labview
Microcontroller
The Plan
• May 16: First Day
• May 21: Project Definition & training (1 week)
• June 5 - June 10: FAE conference in Tucson (1 week)
• July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering,
initial schematic (4 weeks)
• July 14: PCB layout (2 weeks)
• July 21: Basic LabView Coding & Testing preparation (1 week)
• July 29: Initial lab results -Oven(~1 weeks)
• August 3: Accuracy tests (Tucson?)
• August 5: Final Report (2 days)
• August 10: Preliminary Presentation (2 days)
• August 12: Final Presentation (2 days)
• August 18: Last Day (1 week)
Universal Inputs
0-10v and +/- 10v, 0-5v and +/- 5v, 4-20mA
Universal Voltage Input
• 0-5v, 0-10v, +/- 5v and +/- 10v universal voltage input
• Change resistance values to change input voltage levels
• Second order RC filter with poles at 39 Hz and 3900Hz
• Opamp to scale down input
• 2.5v reference generated to scale input
• Opa2333: Low offset voltage and drift, rail-to-rail input, dual opamp part
Noise Calculations: Voltage Reference
• 2.5v Reference
– REF5025: 625nVRMS
enREF 5025  12 (7.5V pp )  625nVRMS
– OPA333: 869 nVRMS
BB noise : 55
nV
Hz
(no 1/f noise)
BWn  (159 Hz )(1.57)  249.63Hz
enBB  (55
nV
Hz
) 249.63Hz  869nVRMS
– Filter KTC noise: 202.8nVRMS
(1.38 1023 KJ )( 298.15k )
en filter 
 202.84nVRMS
100nF
– Reference Output 10kΩ: 202.8 nVRMS
BWn  (159.15Hz )(1.57)  249.9 Hz
enR  4(1.38 1023 KJ )( 298.15k )(10k)( 249.9 Hz )
 202.8nVRMS
– Total Noise: 1.108µVRMS
enREF  (869nV ) 2  2(202.8nV ) 2  (625nV ) 2  1.108VRMS
– Current Noise: 26.34nVRMS (negligible)
enBB  (100
nV
Hz
) 249.63Hz (16.67k)
 26.34nVRMS
Noise Calculations
• Input Filter
– 82nF filter KTC noise: 224 nVRMS
– 820pF filter noise: 211.47 nVRMS
enR  4(1.38 10 23 KJ )( 298.15k )(50k)(38.818Hz )(1.4)
 211.47nVRMS
– Total Noise: 308.5 nVRMS
• Amplifier Noise:
– Feedback Network (16.67kΩ):
828nVRMS
– OPA333 noise: 869.5nVRMS
BB noise : 55
nV
Hz
(no 1/f noise)
BWn  (159.15Hz )(1.57)  249.9 Hz
enBB  (55
nV
Hz
) 249.9 Hz  869.5nVRMS
– Total Noise: 1.2µVRMS
Noise Calculations: Total
• ADC V+ input noise total: 1.503µVRMS
20k
enV   ((1.2)( 120
)1.108V )  ((1.2)( 100kk )308.5nV )  ((1.2)1.2V )  (202.8nV )
 


k 120
 
2
Ref
2
input filter
 1.503VRMS
• ADC V- input noise total:1.089uVRMS
enV   (869nV ) 2  (202.8nV ) 2  (625nV ) 2  1.089VRMS
2
amplifier
output filter
2
Noise Calculations: Bringing it all together
• ADC noise: 1.35 µVRMS
– Noise at Apga =1 and 5 SPS
Ouput noise  (1.35V )  (1.503V )  (1.089V )

  
2
ADC
2
V
 2.295VRMS  13.771VPP
 60bits  0.000358% of FS
V-
2
Resistor Mismatch Errors (Worse Case)
• Resistor Options (worse case)
Set 1
– Set 1: 668.7 µV (0.1% resistors)
VERROR  (1.67v)(
20  0.1% * 20 20

)  668.67 V
100  0.1% * 20 100
Set 2
– Set 2: 3.337 mV (0.1% resistors)
20  20  0.1%
20

)
120  20  0.1%  100  0.1% 100
 3.337mV
VERROR  (1.67v)(
– Set 2: 1.668 mV (0.05% resistors)
20  20  0.05%
20

)
120  20  0.05%  100  0.05% 100
 1.668mV
VERROR  (10v)(
– Set 2:666.8 µV (0.02% resistors)
20  20  0.02%
20

)
120  20  0.02%  100  0.02% 100
 666.8V
VERROR  (10v)(
– Total: 1.797mV
Total Mismatch Gain Error  (668.7 V ) 2  (1.668mV ) 2  1.797mV
Resistor Tolerance Monte Carlo Simulation
• Ran Monte Carlo Simulation
using 0.1% resistors
• 2.5 mV max error on output
• Used an ideal op-amp to
isolate the error source
• Small variation between
resistor tolerances
Error Estimation
• ADC
–
–
–
–
–
6
15µV offset
* 4v  24V
10
INL: 6 ppm
0.0002 * 4v  800V
Gain Error: 0.02%
External Reference: 0.05%*2.024V = 1.024 mV
Total: 1.230 mV
6
• Level shifting OPA2333
–
–
–
–
Offset: 10 µV
Offset drift: 0.05 µV/oc
CMRR

CMRR >106 dB
Vo, cm  AcmVin, cm  Vin, cm Ad 10 20
PSRR: 5 µV/V (max) Vo, PSoffset  VPSnoiseAd PSRR
• 2.5v Reference OPA2333
– Offset: 10 µV
– Offset drift: 0.05 µV/oc
range)
– CMRR >106 dB
– PSRR: 5 µV/V (max)
(3µV over 25oC ± 60oC temperature
Error Estimation
• Resistor Mismatch: 1.797 mV
• REF5025 2.5v reference: 1.25 mV offset is cancelled out
• Total:
V
(1.230mV )  2(10V )  (1.797mV )  2((0.05 o C )(T  25 C ))  2(Vin,cm Ad 10
2
2
2
o
2

CMRR
2
20
)  2(VPSnoiseAd PSRR ) 2
with no “interference”: 2.178 mV
(1.23mV ) 2  (1.797 mV ) 2  2.178mV
Simulation: +/- 10v
Simulation: +/- 5v
Universal Current input
• 4-20mA
• Second order RC filter
• Internal 2.048v reference
• 221Ω shunt converts 4-20mA to 884mV-4.420V
• OPA2333: Rail-to-Rail common mode input, low offset voltage and drift
Simulation
2.5v reference
Differential output
Noise Analysis
• OPA333 buffer noise: 869.5 nVRMS
BB noise : 55
nV
Hz
(no 1/f noise)
BWn  (159.15Hz )(1.57)  249.9 Hz
enBB  (55
nV
Hz
) 249.9 Hz  869.5nVRMS
• Resistor Noise
– 10kΩ: 202.8 nV
– 16kΩ: 123 nV
– 1.6kΩ: 31.1 nV
• V+ Total Noise: 901.8 nVRMS
• V- Total Noise: 1.089 µVRMS (Same as Vinput V-)
enV   (869nV ) 2  (202.8nV ) 2  (625nV ) 2  1.089VRMS
• ADC noise: 1.35 µVRMS
– Noise at Apga =1 and 5 SPS
• Total noise: 11.729 µVPP
Ouput noise  (1.35V )  (901.8nV )  (1.089V )

  
2
ADC
2
V
 1.954VRMS  11.729VPP
 49bits  292 10 6 % of FS
V-
2
Error Estimation
• ADC
–
–
–
–
–
15µV offset
6
* 4v  24V
INL: 6 ppm
106
gain error: 0.02%
0.0002 * 4v  800V
Noise error: 7.78 µVpp
External Reference: 1.024 mV
• Shunt resistor tolerance: 20mA*221*.1% =4.42 mV
• Level shifting OPA333
–
–
–
–
Offset: 10 µV
Offset drift: 0.05 µV/oc
CMRR >106 dB
PSRR: 5 µV/V (min)
Vo, cm  AcmVin, cm  Vin, cm Ad 10
Vo, PS offset  VPSnoiseAd PSRR

CMRR
20
• 2.5v Reference OPA333
–
–
–
–
Offset: 10 µV
Offset drift: 0.05 µV/oc
CMRR >130 dB
PSRR: 2 µV/V
(3µV over 25oC ± 60oC temperature range)
• REF5025: 1.25mV
• Total
V
(839V )  2(10V )  (1.25mV )  (4.2mV )  2((0.05 o C )(T  25 C ))  2(Vin,cm Ad 10
2
2
2
2
o
(839V ) 2  2(10V ) 2  (1.25mV ) 2  (4.2mV ) 2  4.669mV
2

CMRR
2
20
)  2(VPSnoiseAd PSRR ) 2
Temperature Sensors
Thermistor
RTD
Thermocouple
Targeted industrial temperature range: -40oc to 85oc
Thermistor
• Temperature proportional to
resistance
• Calibrated: 25oC and 85oC
• NTC thermistor
– 30kΩ ±1% @ 25oC
 25 / 85  3992  1%
30k
R
1
1
exp( 3992(
 )
398.15k T
• 2 Designs:
– Single-ended
– Bridged
Simulation
Error Estimation
• Resistor Mismatch: 374.81µV
(30k )(30k  30k * .001)
 15k )
60k  30k * .001
 374.81V
ErrorR mismatch  (50A)(
• Current Accuracy:0v
– Ratio metric measurement
• Thermistor Errors: 5.027 mV
(40k )( 40k  40k * .001)
 20k )
80k  40k * .001
 3.731mV
Error thermistor R -  (50A)(
– Thermistor 25oC R-tolerance: 3.731mV (R±1%)
– Beta Error: 3.37 mV (Beta±1%)
Output Voltage Temperature Dependence
800
• ADC Errors:
• Minimum 4.4 mV/oC
• Total Error: 5.425mV (~1.23oC)
700
600
Output Voltage (mV)
– 15µV offset
6
* 2v  12 V
– INL: 6 ppm
106
0.0002 * 2v  400V
– gain error: 0.02%
– External reference R: 2mV
500
B nominal
400
B + 1%
B - 1%
300
200
100
0
0
20
40
60
temp (degrees C)
80
100
Simulation
Error Estimation
• Resistor Mismatch: 1.677mV (0.1% resistors)
(50 A)(30k * .001)  1.5mV
Right : (50 A)(15k * .001)  750 V
Error R mismatch  (1.5mV ) 2  (750V ) 2  1.677 mV
• Current Accuracy: 0v
– Ratio metric reading (external ref)
– Mismatch between current sources:
• ±0.15% of FS (50 µV) = 75nV (negligible)
• Thermistor Errors: 5.027 mV
– Thermistor 25oC R-tolerance: 3.731mV (R±1%)
– Beta Error: 3.37 mV (Beta±1%)
• ADC Errors: 400.5µV
6
* 2v  12 V
106
– 15µV offset
0.0002 * 2v  400V
– INL: 6 ppm
– gain error: 0.02%
• Minimum 4.4 mV/oC
• Total Error: 5.311mV
RTD
• PT100, PT 1000
• Resistance proportional to temperature
• Callendar-Van Dusen equation
Simulation
Error Estimation
• Class A RTD probe: ±0.15oC @ 0oC
• ADC Errors: 400.5µV
–
–
–
–
15µV offset
6
* 2v  12 V
INL: 6 ppm
106
gain error: 0.02% 0.0002 * 2v  400V
External reference tolerance:
ErrorREFERENCE  (100A)( 20k * .001)
 2mV (worst case)
• Total Error: 2.040 mV
Thermocouple
• Seebeck effect
• Need to measure voltage across the element
• Cold junction compensation: RTD close to the cold junction
• PCB layout designed to keep the cold junction isothermal with the RTD
• Types: K, J, T, E, N, R, S, B
• Different materials, temperature ranges, TC
• Example: K type: ~55µV/oC
Error Estimation
•
RTD Error: 2.040 mV
•
Thermocouple element error: Varies by type
•
Max element error (using K type): 1.1oC or 0.4%
Digital Interface
SM-USB-DIG
Stage 2 Interface
• Add MCU
• Excluded from stage
1 (Rev. A)
• MCU controls data
converters
• MCU communicates
through SM-USBDIG to computer
• Adds extra
capabilities
Power
• Powered by a lab
supply for prototyping
• Banana plug input jack
Floor plan
Front-Ends
Control
and Power
The Plan
• May 16: First Day
• May 21: Project Definition & training (1 week)
• June 5 - June 10: FAE conference in Tucson (1 week)
• July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering,
initial schematic (4 weeks)
• July 14: PCB layout (2 weeks)
• July 21: Basic LabView Coding & Testing preparation (1 week)
• July 29: Initial lab results -Oven(~1 weeks)
• August 3: Accuracy tests (Tucson?)
• August 5: Final Report (2 days)
• August 10: Preliminary Presentation (2 days)
• August 12: Final Presentation (2 days)
• August 18: Last Day (1 week)