Download ECE 352 Electronics II

Ch 11 Bipolar Transistors and Digital Circuits
*
2-input ECL OR / NOR Gate
*
*
A
Y = A+B
B
VR
Y = A+B
ECES 352 Winter 2007
*
Ch 11 Bipolar Digital Pt. 1
Examine bipolar junction
transistor (BJT) use in inverters
for logic circuits.
Basic Inverter (RTL)
 One npn transistor and a
load resistor
BJT Inverters
 Transistor-Transistor Logic
(TTL)
 Emitter-Coupled Logic
(ECL)
Analyze to understand inverter
performance:
 voltage transfer
characteristic,
 noise margins,
 fan-in and fan-out limits,
 power dissipation and
 switching speed.
1
Bipolar Transistor Operation
C
VBC _
+
+
V
+
_ CE
_
VBE
E
B
n
Collector
p
Base
n
Emitter
IC
Saturation
IC< β IB
Active
Ic= βIb
* Transistor regions of operation
 Forward Active
VBE > 0 E jnc forward
VBC< 0 C jnc reverse
 Cutoff
VBE < 0 E jnc reverse
VBC < 0 C jnc reverse
 Saturation
VBE > 0 E jnc forward
VBC > 0 C jnc forward
Note: VCE= VBE+VCB
= VBE - VBC
Cutoff IC ≈ 0
ECES 352 Winter 2007
VCE
Ch 11 Bipolar Digital Pt. 1
2
Bipolar Transistor Operation
Transistor regions of operation
*
Forward Active
* Electron injection at emitter and
collection at collector
 VBE > 0 E jnc forward
 VBC< 0 C jnc reverse
 Ic = β Ib
* Cutoff
* No electron injection at Emitter
 VBE < 0 E jnc reverse
 VBC < 0 C jnc reverse
 IC ≈ 0
* Saturation
* Electron injection from both E & C
 VBE > 0 E jnc forward
 VBC > 0 C jnc forward
 IC < β IB
IC
Saturation
IC< β IB
Active
Ic= βIb
Cutoff IC≈0
ECES 352 Winter 2007
VCE
Ch 11 Bipolar Digital Pt. 1
3
Bipolar Transistor Operation - DC
*
*
IC
*
IB
Base bias VBE determines IB
VCC with RC determine output load
line.
Base IB with output load line
determines Quiescent Point (VCE , IC )
Output Load Line
VCC  I C RC  VCE
VCE
VBE
IC
IC 
VCC
RC
IB
VBB
RB
VCC VCE

RC
RC
I B  I Boe qVBE / kT
Base Load Line
VBB  I B RB  VBE
IB 
DC Base
Current
Quiescent
Point
VBB VBE

RR
RB
VCC
VBB
ECES 352 Winter 2007
VCE
VBE
Ch 11 Bipolar Digital Pt. 1
4
Bipolar Transistor Operation – Small Signal AC
iB
iC
vBE
vCE
VBB+vi
* In small signal amplifiers,
 AC signal at input is small –> base current variation is small.
 Device moves around DC quiescent point
 Device stays in the active region
 Amplifier produces current and voltage gain depending upon the
configuration, e.g. common emitter (above).
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1
5
Bipolar Transistor Operation – Digital Circuits
IC
VCC
RC
Saturation
IC< β IB
*
*
Active
Ic=βIb
V
V
CC
CE
Input signal vi is large.
Cutoff IC≈ 0
 VBE and IB changes are large.
 Important applications  digital circuits and power amplifiers
 Device can be in active, saturation or cutoff depending on VBE and IB.
Transistor still operates on the load line.
 Moves from cutoff thru active to saturation or vice versa as the input
signal changes.
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1
6
Bipolar Transistor Operation - Characteristics
*
IC
*
Active
Ic= βIb
Saturation
IC< β IB
*
~ 0.2 V
IB
VCE
Cutoff IC 0
I B  I Boe qVBE / kT
0.7 V 0.8V
ECES 352 Winter 2007
*
Each region of device operation has its
own unique characteristics
Active
 Current gain Ic= β Ib
 VBE = VBE,active ≈ 0.7 V (typical
value)
 VCE,active ≈ ?, NO typical value!
Saturation
 Reduced current gain IC< β IB
 VBE = VBE, sat ≈ 0.8 V (typical value)
 VCE = VCE, sat ≈ 0.2V (typical value)
Cutoff
 No current gain IC ≈ 0, IB ≈ 0
 VBE < O
 VCE,cutoff ≈ ?, NO typical value!
VBE
Ch 11 Bipolar Digital Pt. 1
7
Resistor Transistor Logic (RTL)
*
Y  A B
*
*
*
*
vo
*
vo
vi
RTL Logic
 Earliest and simplest logic
 “0” = low voltage
 “1” = high voltage
Inverter is the basic building bock
Combine two inputs in parallel to
implement NOR
Combine two inputs in series to
implement NAND
Transistors operate in cutoff for
low “0” input (base) voltage, so
IC ≈ 0 and output is high “1”.
Transistors operate in saturation
for high “1” input (base) voltage,
so IC ~ mA’s and the output is
low “0” due to IR drop across RC.
vi
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1
8
Basic Bipolar Transistor Inverter (RTL)
*
*
IB
IC
p
+
VBE
n
n
0.7 V 0.8V
IC
VCC
RC
Active
Ic=βIb
Saturation
IC< β IB
~ 0.2 V
Cutoff IC≈ 0
ECES 352 Winter 2007
Resistor Transistor Logic (RTL)
For low vi input, output vo is high
 Transistor is off (cutoff) since
iB ≈ 0 because base-emitter junction
is not biased sufficiently (VBE is too
small).
 Since iB ≈ 0, then iC ≈ 0 because
iC ≈ β iB.
 So vo = VCC - iC RC ≈ VCC
VBE
* For high vi input, output vo is low
 Transistor is on since iB > 0
because base-emitter junction is
biased sufficiently (VBE is large).
 Since VBE is large (~0.8 V), iB >> 0,
then iC >> 0 since iC ≈ β iB.
 So vo = VCC - iC RC is very small.
 Transistor driven into saturation
region so . vo = VCE,sat ≈ 0.2V
VCE
Ch 11 Bipolar Digital Pt. 1
9
Basic Bipolar Transistor Inverter (RTL)
*
Transistor operates along load line.
V
V
VCC  I C RC  VCE or I C  CC  CE
RC
RC
* Transistor operates in cutoff when
input is low since iB ≈ 0.
* As input vi increases, iB increases
and transistor moves into active
region.
* As input vi increases further,
transistor moves into saturation
region and VCE goes towards zero.
+
+
VCE
VBE
IC
Output Load Line
Input high
vi large
IC
VCC  I C RC  VCE
active
IC 
Saturation
iC/iB < β
VCC VCE

RC
RC
Input low
vi small
0
ECES 352 Winter 2007
cutoff
VCE
Ch 11 Bipolar Digital Pt. 1
10
VCE
RTL Voltage Transfer Characteristic
*
VCC = 5 V
IB
*
+
VCE
+
VBE
0.7 0.8
vo
VBE
*
A B
I
II
Region I (A to B)
 Transistor is in cutoff
 VBE is small, iB ≈ 0, vo = VCC.
Region II (B to C)
 Transistor is on in the active mode
(iC = β iB).
 iB and VBE are larger; VBE ≈ 0.7V
 iC and iB increase as vi and VBE
increase.
 vo and VCE falls as icRC increases.
Region III (C to D)
 Transistor is in the saturation mode
(iC < β iB).
 iB and VBE are larger, VBE ≈ 0.8 V
 iC is larger
 VCE is small, ≈ VCE,sat ≈ 0.2V
III
C
D
vi
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1
11
Noise Margins
Drive
Inverter
*
Load
Inverter
*
*
v01
v02
vi1
*
vi2
Noise margins are a measure of the
reliability of the technology.
Measure of the sensitivity to noise.
Consider one inverter driving an
identical inverter.
How large a noise spike can be
tolerated before an error occurs?
•
v02
v01
•
Load
Inverter
Drive
Inverter
NML
vi1
ECES 352 Winter 2007
VOL VIL
•
NMH
VIH
Ch 11 Bipolar Digital Pt. 1
•
VOH
vi2
For output of driver high
(v01=VOH), then input of load
inverter is high (vi2=VOH ).
A negative noise spike on
input of load inverter
reduces input signal.
Trouble when net input
signal is less than VIH so
noise margin is
NMH = VOH - VIH .
Similarly, for the low state
NML = VIL - VOL .
12
RTL Inverter Noise Margins
VCC = 5 V
*
Noise Margin for Low State
 NML = VIL - VOL
 VIL = VBE,active = 0.7 V
 VOL = VCE,sat = 0.2 V
 NML = VIL - VOL
= 0.7 V - 0.2 V = 0.5 V
*
Noise Margin for High State
 NMH = VOH - VIH
 VOH = VCC = 5 V
 VIH = VBE,sat = 0.8 V
 NMH = VOH - VIH
= 5 V - 0.8 V = 4.2 V
Unequal noise margins for high
and low states.
IB
+
VCE
+
VBE
0.7 0.8
VBE
vo
VOH
A B
I
II
*
III
VOL NML
C
VOL VIL VIH
ECES 352 Winter 2007
NMH
D
vi
VOH
Ch 11 Bipolar Digital Pt. 1
13
RTL Power Dissipation
VCC = 5 V
RC =
10K
IB
*
+
VCE
+
*
VBE
0.7 0.8
VBE
vo
A B
VOH
I
II
Output High State (Low input)
 Transistor is in cutoff so iC  0.
 No static power dissipation for
high state, PH = 0.
Output Low State (High input)
 Transistor is in saturation so
v o = VCE,sat = 0.2 V.
 iC = (VCC - VCE,sat )/RC
= (5V - 0.2 V)/10K = 0.48 mA.
 PL =VCC iC = (5 V)(0.48 mA)
= 2.4 mW
 Average P = 1/2(PH + PL)
= 1.2 mW
III
C
VOL
D
vi
VIL
VIH
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1
14
RTL Propagation Delay
*
VCC = 5 V
Output going high
iR

iCap

VCC
+
+
vo
C
VCE
+
VBE
iCap  iCap (t )  C
VCE,sat
tPLH

VCE ,sat
dvo
V  vo (t )
 iR  CC
dt
RC
t
dvo
1

dt
VCC  vo RC C 0
t 
t
t 
t






RC C
RC C
RC C
RC C




vo  VCC 1  e
 VCE , sat e
 5V 1  e
 0.2V e








t PLH  time for output to rise to
A B
I
vo
t
vo
VOH
Transistor turned off (cutoff)
Charging current flows through RC
tPLH is time it takes the output to
rise from VOL = VCE,sat = 0.2 V to
1/2(VOH + VOL) = 2.6 V

vo
II
1
VOH  VOL   1 5V  0.2V   2.6V
2
2
t
t

 PLH 
 PLH
R
C
C
  0.2V e RC C
2.6V  5V 1  e




vo 
III
C
VOL

vi
VIL
VIH
ECES 352 Winter 2007
5  2 .6
 0.5
4.8
For R C  10K and C  10pF we get
e
D
t PLH
RC C

Long
charge – up
time!
t PLH  RC C ln 2  10 K (10 pF )  1.x10 7 sec  100 n sec
Ch 11 Bipolar Digital Pt. 1
15
RTL Propagation Delay
*
VCC=5V
Output going high

vo
iR

iCap

VCC
+
+
vo
C
Transistor turned off (cutoff) (M  N)
Charging current flows through RC
tPLH is time it takes the output to rise
from VOL = VCE,sat = 0.2 V to
1/2(VOH + VOL) = 2.6 V (N  O)
VCE
+
VCE,sat
VBE
tPLH
t
Transient Response
MNO
vo
A B
VOH
I
IC
II
M
III
C
VOL
D
vi
VIL
VIH
ECES 352 Winter 2007
P
N
Ch 11 Bipolar Digital Pt. 1
VCE
O
16
RTL Propagation Delay
*
VCC = 5 V

vo
iR
Output going low
iCap

VCC
+
+
+
vo

C
VCE
VBE
Transistor turned on (saturation)
and providing discharge current
(P R)
But current also flows through RC
tPHL is time it takes the output to
fall from VOH = VCC = 5 V to
1/2(VOH + VOL) = 2.6 V (R  S)
VCE,sat
tPHL
t
vo
A B
VOH
I
IC
II
Transient Response
PRS
S
R
III
C
VOL
D
vi
VIL
VIH
ECES 352 Winter 2007
P
VCE
Ch 11 Bipolar Digital Pt. 1
17
RTL Propagation Delay
*
VCC = 5 V
iCap
iR
iCap
+
+
VBE
+
vo
Output going low
dv
V  vo
 C o  iR  iC  CC
 iC so
dt
RC
vo

VOH
t
VCC
dvo
1

dt
 vo  iC RC RC C 0
Assuming a constant transistor current, then
C
VCE
vo  VCC
t 
t
t 
t






RC C
RC C
RC C
RC C
  VOH e
  5V e
 iC RC 1  e
 (5V  iC RC ) 1  e








t PHL  time for output to fall from VOH  5V to vo  2.6V
t
t
t

 PHL 
 PHL
 PHL
R
C
R
C
C
C
  5V e
2.6V  (5V  iC RC ) 1  e
 (5V  iC RC )  iC RC e RC C





e
IC
t PHL
RC C

 i R

iC RC  2.4
so t PHL  RC C ln  C C 
iC RC
 iC RC  2.4 
For a transist or with   50 and R B  100 K ,
iB 
S
RB

5V  0.7V
 43A and iC   iB  50(43A)  2.15 mA
100 K
For R C  10K and C  10pF we get
R
P
VCE
ECES 352 Winter 2007
vi  VBE ,act
 2.15mA(10 K ) 
t PHL  RC C ln 
 1.1x10 8 sec  11 n sec

 2.15mA(10 K )  2.4 
Short
1
t P  100 n sec  11 n sec   56 n sec
discharge
2
time!
DP  t P P  56 n sec 1.2mW   67 pJ
Ch 11 Bipolar Digital Pt. 1
18
Resistor Transistor Logic (RTL)
* RTL provides simple, basic digital
technology based on bipolar
transistors and resistors.
• Logic levels and noise margins
Y  A B
Noise Margin for Low State
 NML = VIL – VO
= 0.7 V - 0.2 V = 0.5 V
 Noise Margin for High State
 NMH = VOH - VIH
= 5 V - 0.8 V = 4.2 V
 Unequal noise margins for high
and low states.
Propagation delays
t PHL  11 n sec
 Output going low
 Output going high t PLH  100 n sec
t P  56 n sec
 Propagation delay
Power – Delay Product

vo
*
vo
vi
*
vi
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 1


DP  t P P  56 n sec 1.2mW   67 pJ
19