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The Devices Jan M. Rabaey Digital Integrated Circuits Introduction © Prentice Hall 1995 Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends Digital Integrated Circuits Introduction © Prentice Hall 1995 The Diode B A Al SiO2 p n Cross-section of pn-junction in an IC process A Al A p n B B One-dimensional representation Digital Integrated Circuits diode symbol Introduction © Prentice Hall 1995 Depletion Region hole diffusion electron diffusion p (a) Current flow. n hole drift electron drift Charge Density + x Distance - Electrical Field (b) Charge density. x (c) Electric field. V Potential -W 1 Digital Integrated Circuits W2 Introduction x (d) Electrostatic potential. © Prentice Hall 1995 Diode Current Digital Integrated Circuits Introduction © Prentice Hall 1995 Models for Manual Analysis + ID = IS(eV D/T – 1) VD ID + + VD – – (a) Ideal diode model Digital Integrated Circuits – VDon (b) First-order diode model Introduction © Prentice Hall 1995 Junction Capacitance Digital Integrated Circuits Introduction © Prentice Hall 1995 Diode Switching Time Rsrc VD V1 ID Vsrc V2 t=0 t=T VD Excess charge Space charge ON OFF ON Time Digital Integrated Circuits Introduction © Prentice Hall 1995 Secondary Effects ID (A) 0.1 0 –0.1 –25.0 –15.0 –5.0 0 5.0 VD (V) Avalanche Breakdown Digital Integrated Circuits Introduction © Prentice Hall 1995 Diode Model RS + VD ID CD - Digital Integrated Circuits Introduction © Prentice Hall 1995 SPICE Parameters Digital Integrated Circuits Introduction © Prentice Hall 1995 The MOS Transistor Gate Oxyde Gate Source Polysilicon n+ Drain n+ p-substrate Field-Oxyde (SiO2) p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Digital Integrated Circuits Introduction © Prentice Hall 1995 Cross-Section of CMOS Technology Digital Integrated Circuits Introduction © Prentice Hall 1995 MOS transistors Types and Symbols D D G G S S NMOS Enhancement NMOS Depletion D D G G S S PMOS Enhancement Digital Integrated Circuits B Introduction NMOS with Bulk Contact © Prentice Hall 1995 Transistor: No Voltages Gate Oxyde Gate Source Polysilicon n+ Drain n+ p-substrate Field-Oxyde (SiO2) p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Digital Integrated Circuits Introduction © Prentice Hall 1995 Transistor “Off” Vgs<Vt + S VGS - D G Ids n+ n+ n-channel Vgd Depletion Region R Vgs p-substrate B Ids No Channel exists: Enhancement mode transistor I=V/R Vds does not matter Vds Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Threshold Voltage: Concept + S VGS - D G n+ n+ n-channel Depletion Region p-substrate B Digital Integrated Circuits Introduction © Prentice Hall 1995 The Threshold Voltage Body Effect Out A ? B GND Digital Integrated Circuits Introduction © Prentice Hall 1995 Channel Formation Vgs>Vt + S VGS - D G Ids n+ n+ n-channel Vgd Depletion Region Vgs p-substrate R B Positive Charge on Gate: Channel exists, but no current since Vds = 0 Ids I=V/R Vds Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Current-Voltage Relations VGS VDS S G n+ – V(x) ID D n+ + L x p-substrate B MOS transistor and its bias conditions Digital Integrated Circuits Introduction © Prentice Hall 1995 Linear Region Vgs>Vt & Vgd>Vt + S VGS - D G Ids n+ Vgd n+ n-channel Depletion Region R Vgs p-substrate B Positive Charge on Gate: Channel exists, Current Flows since Vds > 0 Ids = k’(W/L)((Vgs-Vt)Vds-Vds2/2) Ids I=V/R R= 1/(k’(W/L)(Vgs-Vt)) Vds Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Transistor in Saturation VGS VDS > VGS - VT G D S n+ Digital Integrated Circuits - VGS - VT Introduction + n+ © Prentice Hall 1995 Saturation: Vgs>Vt & Vgd<Vt + S VGS - D G Ids n+ Vgd n+ n-channel Depletion Region Vgs p-substrate Ids B Positive Charge on Gate: Channel exists, Current Flows since Vds > 0 But: channel is “pinched off” Ids = (k’/2)(W/L)(Vgs-Vt)2 Introduction to VLSI Design Ids Introduction Vgs “constant current source” Vds © Steven P. Levitan 1998 Current-Voltage Relations Digital Integrated Circuits Introduction © Prentice Hall 1995 I-V Relation VDS = VGS-VT Saturation ID (mA) VGS = 4V 1 0.0 VGS = 3V 1.0 2.0 3.0 VDS (V) VGS = 2V VGS = 1V 4.0 5.0 0.020 ÷ID Triode Square Dependence 2 VGS = 5V 0.010 Subthreshold Current 0.0 2.0 VT1.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5V). (a) ID as a function of VD S NMOS Enhancement Transistor: W = 100 m, L = 20 m Digital Integrated Circuits Introduction © Prentice Hall 1995 A model for manual analysis Digital Integrated Circuits Introduction © Prentice Hall 1995 Saturation Effects Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor. Which is the resistor? Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Regions of Operation Summary REGION NMOS Vtn = .7v k’ = 80A/V2 PMOS Vtp = -.7v k’ = 27mA/V2 Off Vgs<Vtn Ids=0 Vgs>Vtp Ids=0 Linear Vgs>Vtn & Vgd>Vtn Vgs<Vt & Vgd<Vtp Ids= k’(W/L)(Vgs-Vt)Vds-Vds2/2) Saturation Vgs>Vtn & Vgd<Vtn Vgs<Vtp & Vgd>Vtp Ids= (k’/2)(W/L)(Vgs-Vt)2(1+Vds) Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Computed Curves Linear Resistor Vgs = 5v Vgs = 4.5v Vgs = 4.0v Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Spice Curves Vgs = 5v Vgs = 4v Vgs = 3v Vgs = 2v Vgs = 1v Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Fitting level-1 model for manual analysis Region of matching ID Short-channel I-V curve VGS = 5 V Long-channel approximation VDS = 5 V VDS Select k’ and such that best matching is obtained @ Vgs= Vds = VDD Digital Integrated Circuits Introduction © Prentice Hall 1995 Retrofitted Level 1 Parameters 1.2um CMOS NMOS » VTO = 0.743 V » K’ = 19.6 A/V2 (20 vs 80) = 0.06 V-1 PMOS » VTO = -0.739 V » K’ = 5.4 A/V2 (5 vs 27) = 0.19 V-1 Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Dynamic Behavior of MOS Transistor G CGS CGD D S CGB CSB CDB B Digital Integrated Circuits Introduction © Prentice Hall 1995 The Gate Capacitance Digital Integrated Circuits Introduction © Prentice Hall 1995 Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off Digital Integrated Circuits Introduction © Prentice Hall 1995 Diffusion Capacitance Digital Integrated Circuits Introduction © Prentice Hall 1995 The Sub-Micron MOS Transistor • Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup Digital Integrated Circuits Introduction © Prentice Hall 1995 Parasitic Resistances Polysilicon gate LD G Drain contact W VGS,eff D S RS RD Drain Digital Integrated Circuits Introduction © Prentice Hall 1995 Velocity Saturation (2) 1.5 0.5 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 VDS 3.0 (V) 4.0 5.0 (a) I D as a function of VDS ID (mA) VGS = 4 I D (mA) 1.0 Linea r Dependence VGS = 5 0 0.0 1.0 2.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5 V). Linear Dependence on VGS Digital Integrated Circuits Introduction © Prentice Hall 1995 Sub-Threshold Conduction 102 ln(ID) (A) 104 Linear region 106 108 1010 10120.0 Digital Integrated Circuits Subthreshold exponential region VT 1.0 2.0 3.0 VGS (V) Introduction © Prentice Hall 1995 Latchup VD D VDD p + n + + n + p + + p n-well p-source n Rnwell Rpsubs n-source p-substrate (a) Origin of latchup Digital Integrated Circuits Rnwell Introduction Rpsubs (b) Equivalent circuit © Prentice Hall 1995 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular Digital Integrated Circuits Introduction © Prentice Hall 1995 MAIN MOS SPICE PARAMETERS Digital Integrated Circuits Introduction © Prentice Hall 1995 SPICE Parameters for Parasitics Digital Integrated Circuits Introduction © Prentice Hall 1995 SPICE Transistors Parameters Digital Integrated Circuits Introduction © Prentice Hall 1995 Technology Evolution Digital Integrated Circuits Introduction © Prentice Hall 1995 Spice Parameters for Parasitics Digital Integrated Circuits Introduction © Prentice Hall 1995 Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices. Digital Integrated Circuits Introduction © Prentice Hall 1995 Impact of Device Variations 2.10 2.10 Delay (nsec) Delay (nsec) 1.90 1.90 1.70 1.70 1.50 1.10 1.20 1.30 1.40 1.50 1.60 1.50 –0.90 Leff (in mm) –0.80 –0.70 –0.60 –0.50 VTp (V) Delay of Adder circuit as a function of variations in L and VT Digital Integrated Circuits Introduction © Prentice Hall 1995
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