Download I3T Modeling - MOS-AK

Modeling flow and models improvement for I3T
ON Semiconductor technologies
Petr Betak, Petr Zavrel, Lenka Sochova, Jan Plojhar
MOS-AK September 2011
I3T Modeling flow : September-2011
Overview
•
•
•
•
•
OVERVIEW: ON technologies
WHAT IS MODELING
GENERAL FLOW IN MODELING
 Data For Modeling Purpose
 Built up model card as a subcircuit
DEVICES (focus on I3T80 & I3T50)
 CMOS
 DMOS
 BIPOLARS
 DIODES
 RESISTORS
 CAPACITORS
SPECIAL CASES, MODEL IMPROVEMENT
I3T Modeling flow: September-2011
Overview: ON technologies
Bipolar : BIP14V, BIP18V, BIP30V, BIP50V, ON50 ...
BCD : ONC25 (0.25um) , PS5, AIM
Analog CMOS: ACMOS, ONC110 (0.11um), ONC18
(0.18um), ONC25(0.25um)
VHVIC (very high voltage) analog CMOS
BCDMOS: I2T100 (0.7um)
I3Txx: I3T25, I3T50, I3T80 (0.35um)
C3, C5 (0.35um, 0.5um)
Special: Low Vf Rectifiers, Integrated Power devices, HV
FET, Microintegration ...
I3T Modeling flow: September-2011
WHAT IS MODELING?
DEVICE
EQUATIONS
ENM (with Nepi terminal)
D
G
S
N+
B
Nepi
P+
PWELL
p-sub
P+
Psinker
N-epi
BLP
p-substrate
•
•
•
…..
MODEL
enm (d g s b) enm_model w=10 l=0.8
model
enm_model bsim3v3 type=n
+ vth0 = 0.582
+ u0 = 290
+ rdsw = 749.6872
+ tox = 7.10e-9
+ vsat = 5.55e4
+ k1 = 0.55
+ dvt0 = 10.7
+ cj = 1.02e-3
+ cjsw = 3.11e-10
+ cjswg = enm_cjswg
+ js = 3.5e-7
+ jsw = 5e-13
…….
DEVICE MODEL - set of mathematical relations between node voltages and
terminal currents
GOAL - accurately represent electrical behavior in circuit simulators
DEPENDEND ON DIFFERENT KIND OF PARAMETERS:
– technology parameters
– geometry (layout) parameters
– empirical (fitting) parameters
I3T Modeling flow: September-2011
GENERAL FLOW IN MODELING
Building up the model card
as a sub circuit
Data for Modeling Purpose
DC :
•
IV curves
•
mismatch
•
junction leakage, substrate
leakage
Testchip
•WL arrays
•Matching frames
•RF frames
•
process variation
AC low frequency:
•
junction capacitance
•
low frequency noise
1/ Model extraction of the main
device - ICCAP,UTMOST, Matlab,
Perl routines are used for
optimization purpose
2/ Adding models of the
parasitic component
3/ Building up corners
(3 corners)
4/ Implementation of the SOA
flags based on Reliability
inputs
5/ Implementation of the
matching parameter into the
model
6/ Model of ESD cells
I3T Modeling flow: September-2011
Model Kit &
test
Running basic and
specific tests
at device level
(simulate a netlist)
and at circuit level
(simulation of
schematic in
Design
Environment)
Data For Modeling Purpose
 DC MEASUREMENT DATA
measured on golden wafers of different lots:
IV curves, transforms
temperature sweeps
different dimensions (W,L matrix)
 CV MEASUREMENT DATA
measured on golden wafers of different lots:
CV curves, junction capacitances
frequency sweeps
different dimensions (W,L matrix)
 S PARAMETERS DATA
measured on golden wafers of different lots:
 capacitance extraction
 high frequency verification
 NOISE measurement, matching extraction ...
I3T Modeling flow: September-2011
Built up model card as a subcircuit
STANDARD MODEL
(BIPOLAR-VBIC,MOS -BSIM3V3..)
1/ Model extraction of the
main device - ICCAP,UTMOST,
Matlab, Perl routines are used for
optimization purpose
2/ Adding models of the
parasitic component
3/ Building up process
corners
(3 corners)
4.5
25 years
10 years
1 year
1e6s
1e5s
1e4s
Forbidden region
4
3.5
VGS (V)
3
2.5
5/ Implementation of the
matching parameter into the
model
2
1.5
1
6/ Model of ESD cells
0.5
0
0
4/ Implementation of the
SOA flags based on Reliability
inputs
10
20
30
VDS (V)
40
50
I3T Modeling flow: September-2011
fast
0.0004
0.00035
typical
0.0003
ID (A)
MACROMODEL= several standard model devices
(DMOS –DMOS AMIS MACROMODEL..)
0.00045
slow
0.00025
0.0002
0.00015
0.0001
0.00005
0
0
2
4
6
8
10
VGS (V)
Difference between identically
designed analogue devices is
modelled on the base of
PELGROM FORMULA:
2 
A2
 S 2C 2
WL
12
I3T80 & I3T50 DEVICES
Short overview of model features &
limitations per device groups:
• Low Voltage MOS
• High Voltage MOS
• Bipolar Transistors
• Diodes
• Resistors
• Capacitors
I3T Modeling flow: September-2011
Low Voltage MOS
Model Features:
DEVICE
ENM (with Nepi terminal)
D
G
S
B
N+
Nepi
p-sub
P+
P+
PWELL
Psinker
N-epi
•BSIM 3v3, BSIM4 model
•SOA, Matching
•DC (geom., temp., leakage)
• AC (CV + 1/f noise)
•Multi-fab / process corners
•Verified till 200C
BLP
p-substrate
Model Limitations:
Nepi strap
+
30.00
25.00
20.00
Gm/Id_meas
15.00
Gm/Id_sim
10.00
5.00
Vgs (V)
P-substrate
Pocket Diode:
•NEPI-to-PSUB (NLVD, NMVD)
I3T Modeling flow: September-2011
1.11
1.01
0.91
0.81
0.71
0.61
0.51
0.41
0.31
0.01
0.00
0.21
nmos
35.00
0.11
MODEL
Gm/Id vs Vgs
W/L=20/20 VDS=0.5 VBS=0 TEMP=27C
Gm/Id (1/V)
•Moderate/weak
inversion inaccuracy
•Incapable of
RF modeling
High Voltage MOS
DEVICE
channel
region
drift
region
MODEL
Model Features
•JFET(J1) for drift region
(model IDSAT & Ron)
•Standard BSIM3v3 dominant MOS
(M1) model channel part (VTH & BETA)
•AC behaviour modelled by dominant MOS
& added shorted MOSFETs (M2 & M3)
•Parasitic diode integrated in subcircuit
•Formula for BLN res.
•SOA, Matching
•Verified till 200C
•1/f noise
Gate
M1
M2
M3
Source
Drain
D1
J1
D2
D3
Nepi
+
•Limitations
•No parasitic BJT
•No self-heating
•AC modelled at 100kHz
Pocket diode
•NEPI/BLN-to-PSUB
Bulk
Substrate
I3T Modeling flow: September-2011
MOS & DMOS
•
DC MODELING
– IDVG over temp. and over size
– VTH, short & narrow channel
effect
– Body effect
– IDVD over temp. and over size
– IDSAT & RON over size
NMOS short channel effect
Ron
IDSAT
lfpdm80 output curves
I3T Modeling flow: September-2011
MOS & DMOS
• Vth & Beta Matching
A

2
VT
 VT 2  
 CV2 

 WL

T
• AC
– Cgs,
Cgd over size
for different
VG & VD
INTRINSIC
ACCUMULATION MOSFET
MOSFET
AVT  9.1729 mV .m
CVT  0 mV
R 2  95 .8 %
I3T Modeling flow: September-2011
• 1/f noise
Bipolar Transistors
Model Features:
•VBIC (NPN) model & BJT (PNP)
•Vertical devices
•Checked till 200C

N+ guard ring
DC
P+
N+
Pfield
Gummel
Poon (+ Beta vs. Ic)
Output characteristics (+ Early Voltage)
Validated on band-gaps (∆VBE tuned)
Base-emitor breakdown and parasitic PNP (for NPN)

E
AC
diffusion
and
depletion capacitances
•Matching
 I E   I s
 ,  

 IE   Is
 
  
,  

  



Model Limitations
•No S-param validation
•No 1/f noise
I3T Modeling flow: September-2011
B
C
p-sub
SIPROT
Nplug
P+
P+
Psinker
N-epi
BLP
BLN
BLN
p-substrate
Diodes / Junctions
Model Features:
FORWARD
•DC
- forward
- Breakdown & leakage
- done for -30C till 200C
•AC (capacity modelled)
•SOA
•Based on diode, dio500 standard models
Model Limitations:
•Transit-time model=charged based
model, not accurate enough
•Parasitic bipolar not modelled
•Snap-back not modelled for ESD diodes
I3T Modeling flow: September-2011
BREAKDOWN & LEAKAGE
CAPACITANCE
Resistors
Model Features:
•POLY ,Diff. Resistors ,METAL RESISTORS
sheet res.
R  Rsh *
L  2 * EtchL
* (1  Tc1 * (T  Tnom )  Tc 2 * (T  Tnom ) 2 )
W  2 * Etch
temperature dep.
correction
•matching based on Pelgrom formula
for resistance std. deviation
•based on phy_res, resistor,
bsource standard models
•verified form -40C till 200C
Model Limitations:
•TC not modelled over corners & over size
•TC based on typical silicon,
only PPOR statistically verified
I3T Modeling flow: September-2011
Capacitors
Model features:
•MIM capacitor, metal to metal cap., horizontal bar & plate cap.
•Voltage linearity and temperature dependency model (TC)
•Scalable according the bar, width & length
•Verified till 125C
•SOA implemented
Model limitations:
•no matching in the models
•minimum dimension of device at least 10um
•resistance & self inductance not included
I3T Modeling flow: September-2011
MIMC
Special cases, model improvement
Model conversion into different simulator language
SPECTRE, ELDO, HSPICE:
-> HSPICE model of the physical resistor
Modeling of the substrate current and recovery charge:
JUNCTION DIODES:
-> Enhanced NQS Lauritzen diode model
I3T Modeling flow: September-2011
HSPICE model of the physical resistor
Circuit connection of the model
elements in HSPICE for SPECTRE
“subtype=p”
Circuit connection of the model
elements in HSPICE for SPECTRE
“subtype=poly”
C SPECTRE  C1  C 2
Circuit connection of the model
elements in HSPICE for
SPECTRE “subtype=n”
I3T Modeling flow: September-2011
HSPICE model of the physical resistor
Example of the Physical resistor
conversion
Comparison of the SPECTRE and HSPICE
results
Discrepancy between SPECTRE and HSPICE results
0,0045
0,004
0,0035
Discrepancy (%)
0,003
0,0025
L=10um
0,002
L=100um
L=1000um
0,0015
0,001
0,0005
0
0
0,5
1
1,5
2
-0,0005
Voltage (V)
I3T Modeling flow: September-2011
2,5
3
3,5
ENHANCED NQS LAURITZEN DIODE MODEL
MAIN DIODE:
•NQS diode verilog model for AK diode
(dioAREAmain and dioPERImain)
•substrate current source model
IPsub=f(IA)
•breakdown diode (SPICE)
PARA DIODE (POCKET DIODE):
•NQS diode verilog model for KPsub
diode
•current source model lAPsub=f(IPsub)
•breakdown diode (SPICE)
I3T Modeling flow: September-2011
ENHANCED NQS LAURITZEN DIODE MODEL
Reverse recovery effect modeling
Extraction of diffusion capacity
The indirect approach of tuning and measuring reverse
recovery effect consists in measuring S-parameters and
extraction of a diffusion capacitance of forward biased
diode in the area of threshold voltage region
(OFF state to ON state) with the voltage step of 5 mV
[3].
Comparison of current in time during recovery for measured diode
(ia.m - blue) and NQS Lauritzen updated model (ia.s - cyan)
tau,tt
NQS updated Lauritzen model (blue) vs. measured
(extracted) diffusion capacity (cyan)
I3T Modeling flow: September-2011
ENHANCED NQS LAURITZEN DIODE MODEL
Current source model
The current source IPsub:
• model of the substrate current dependent on
current flowing through the MAIN DIODE(IA)
•expressed by (1), where m=1.606 and n= -5e-3
are variables to tune the current behavior,
determined based on measurement data
Conclusion
IPsub [A]
IPsub vs. IA w=50um & T=30C
1,8E-03
1,6E-03
1,4E-03
1,2E-03
1,0E-03
8,0E-04
6,0E-04
4,0E-04
2,0E-04
0,0E+00
0,0E+00 5,0E-03 1,0E-02 1,5E-02 2,0E-02 2,5E-02
IA [A]
IPsub_measured
ISUB_w50_w12 data
IPsub_model data
ISUB_w50_w11_sim
IPsub  IAm  n  IA
I3T Modeling flow: September-2011
The current added by PARA DIODE to MAIN
DIODE IAsub=g(IPsub) is lower level of
magnitude, ca. 0.1% of MAIN DIODE IA stream
ad is of same model where n= -66e-6 & m=5.163
(1)
•The proposed macro-model of diode enhances the
standard diode model by adding Lauritzen NQS model of
reverse recovery effect and the model of the diode
cathode-to-substrate junction.
• The updated macro-model of the diode visibly improves
reverse recovery effect simulation results.
•The proposed model of substrate current also fits well
the measured data as well as reverse current from
measured at the substrate node.
• What is also positive point, the updated NQS model of
investigated diode do not leads to convergence problem
and do not increase simulation time.
REFERENCES
[1] P.O Lauritzen, C.L. Ma, “A Simple Diode Model with Reverse Recovery”,
IEEE Transaction on Power Electronics, Volume 6, Issue 2, April 1991, pp.
188-191
[2] Sauter Martin, “Reverse Recovery Effects in SPT5 Diodes”, Infineon
Technologies papers, IC-CAP Modeling Handbook, internet source:
http://edocs.soco.agilent.com/pages/viewpage.action?pageId=105321342
[3] Sischka Franz, “IC-CAP Learning Week”, Agilent Technologies, EEsoft EDA
Europe, May 2010
[4] A.Vladimirescu, The Spice Book New Yorl, 1994, John Wiley & Sons, Inc
[5] Cadence Circuit Components and Device Models Manual Product Version
6.1, December 2006, CADENCE
[6] HSPICE Reference Manual: Elements and Device Models Version C-200909, September 2009,. SYNOPSYS
[7] ELDO Users’s Manual Software version 6.10_2 Release AMS 2007.2a,
2007,. MENTOR GRAPHICS CORP.
[8] Stanislav Banas, et al. “Enhanced NQS Lauritzen Diode Model”, MIXDES,
2011, Proceedings of the 18th International Conference, pp. 82-84
I3T Modeling flow: September-2011