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Punch-through location in ATLAS SCT sensors
Outline
1.
2.
3.
4.
5.
Introduction
Electrical measurements
Thermal Imaging Studies
Conclusions
Appendix
A.Chilingarov, Lancaster University, UK
B.Hommels, Cambridge University, UK
A.Weidberg, Oxford University, UK
A. Chilingarov, A. Weidberg, Bart Hommels
PTP location studies – AUW 20/04/2010, DESY
1. Introduction
• The punch-through protection (PTP) in the p-in-n SCT sensors
is more simple than that in the n-in-p Upgrade sensors and
therefore should be easier to understand.
• On the one hand this understanding is important for predicting
the SCT sensors behaviour under heavy flux of particles (e.g.
during a beam splash).
• On the other hand it may shed a light on the puzzles observed
in the PT operation of the Upgrade sensors (e.g. almost
identical PT operation of the sensors with and without special
PTP structures).
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
2
A
Rb
Rstr
e
Rdyn
In a typical measurement a DC potential,
Ustrip, is applied to the strip implant near
bias resistor and the resulting current,
Istrip, is measured. The slope dUs/dIs
gives an effective dynamic resistance,
Reff, between the strip and the bias rail.
In the above case the Reff consists of the bias resistor, Rb, with Rdyn + Rstr in
parallel. Here Rdyn is the dynamic resistance of the 8 mm punch-through gap at
the side opposite to the bias resistor (far side). Above the PT onset voltage Rdyn
decreases quickly with Ustrip. If the PT develops only at the far side, the strip
implant resistance Rstr of ~ 500 kW should limit Reff at Rb||Rstr value of ~ 400kW.
Since the PT gap at the bias resistor side (near side) is ~30 mm it was usually
assumed that the PT develops mainly at the far side.
The quoted gap dimensions are from Hamamatsu (courtesy of Nobu Unno).
The photographs made recently at Cambridge confirmed a strong PTP gap
asymmetry.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
3
SCT sensor strip Geometry: far side
End cap sensor, far side of the strip.
Barrel sensor, far side of the strip.
All dimensions are in microns.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
4
SCT sensor strip Geometry: near side
End cap sensor, near side of the strip.
Barrel sensor, near side of the strip.
All dimensions are in microns.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
5
Lancaster 9-14.05.07: strips with highest Up-through in 7 SCT sensors
dU/dI (kW)
1000
However it was long time
known that the dynamic
resistance in the PT
measurements drops well
below the expected
saturation level of ~400 kW.
In this example the results
are shown for 7 end-cap
sensors of different types.
100
w12-406
w21-9
w22-18
w31-225
w31-405
w31-1277
w32-560
10
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
Ubias (V)
There may be two possible explanation of such a behaviour. Either the strip implant
resistance is much lower than the value of ~500 kW given by Hamamatsu (via Nobu Unno)
or the PT develops also at the resistor side and with a similar onset voltage.
To clarify this situation the dedicated measurements were performed recently with several
barrel sensors which in contrast to the end-cap sensors allow the strip implant access at
both sides of the strip.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
6
2. Electrical measurements
B-4098 after 67 hours at 150V, strip 427
Lancaster, December 2009
Rbias
To study the PT at the near
and far side of the strip
separately the strip edge
opposite to that of the test
voltage application was
grounded.
1000
dU/dI, kW
Rstrip
Rstrip|| Rbias
100
far only
near only
near&far
10
0
2
4
6
8
10
12
Ustrip, V
14
16
18
20
22
Corresponding curves are
labelled as “far (near) only”.
For reference purposes a
standard measurement with
the Ustrip applied at the near
side with the far side floating
was also made (“near&far”
curve).
For the Ustrip applied at the far side the initial plateau resistance is at 507 kW level in agreement
with the expected implant resistance value. When the Ustrip is applied at the near side the
plateau is at 1480 kW (representing Rbias) if the far edge is floating and at 387 kW for the far
edge grounded (“near only” case). The latter number is close to 1480 kW || 507 kW. Obviously
the PT develops at both edges of the strip.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
7
Lancaster, December 2009
B-4098 after 67 hours at 150V, strip 427
Subtracting the ohmic current
Ustrip*Rplateau from the total current
allows calculation of the PT
current. The results are shown for
the same measurement
configurations as in the previous
slide.
3.0
far only
near only
near&far
2.5
PT current, mA
2.0
1.5
1.0
0.5
0.0
8
9
10
11
12
Ustrip, V
13
14
15
Surprisingly the PT onset for the
near side alone (~9.5V) is lower
than that for the far side alone
(~11.5V) in spite of a much larger
PT gap at the near side. For the
“near&far” case the current follows
exactly the pattern of “near only”
current up to 11.5V where an
additional contribution from the PT
at the far side appears.
By separate measurements it was proven that the PT current doesn’t “leak” to neighbouring
strips but flows directly to the bias rail. The details of these measurements can be found in the
Appendix to this talk.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
8
3. Thermal Imaging Studies
Simulation of thermal excess as a result of PTP breakdown (S. Yang, Oxford):
Geometry:
Silicon plate: 60mm x 60mm x 0.3mm
Heat source:
0.02mm x 0.02mm x 0.005mm, -- case 1
0.02mm x 0.02mm x 0.01mm, -- case 2
0.02mm x 0.02mm x 0.02mm, -- case 3
Loading conditions:
Heat source total power: 0.001 Watts.
Boundary conditions:
Applied convection coefficient of 2.5E-5 W/mm^2-C (still air)
to the top face of Silicon plate.
a: assume all other surfaces are adiabatic boundary
condition.
b: fixed temperature at other faces at 20 deg C.
Results:
=> Best-case temperature rise: 0.16K
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
As the expected temperature rise due to PTP breakdown is tiny, the best
place one could hope to observe it would be the far end, where the PTP
gap is only 8µm. The IR imaging resolution has to match the gap size, as
the proximity of metal surfaces will equalize any temperature excess.
On the Rbias side, thermal effects originating from the PTP gap will be
obfuscated by the Poly-Si layer stacked on top of it.
Attempts were made to confirm PTP using sensitive IR imaging equipment
(thanks to G. Villani, RAL) , at ~40x increased power dissipation. It was
confirmed that measuring such a small thermal excess is a non-trivial
affair, however.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
Conclusions
1.
In the SCT sensors the punch-through happens at both edges of
the strip. Therefore the PT current is not limited by the strip
implant resistance of ~500 kW.
2.
Near the bias resistor the PT gap is several times larger than that
at the opposite (far) side. Nevertheless the PT onset voltage at
the near side is lower than at the far side. It would be very useful
to understand the reasons for this.
3.
The PT current doesn’t leak to neighbouring strip but flows
directly to the bias rail.
3.
It was found quite difficult to pin-point the PT location with the
help of the infra-red camera.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
11
5. Appendix: PT “leak” study
Lancaster, January 2010
B4098: Pth scans with master strip 400 on 29.1.10
90
80
15:23
15:26
15:29
15:31
Vm/Rbias
70
60
Imaster, mA
The method is based on the
interstrip resistance
measurement technique. The
potential called Vmaster is
applied to the implant of the
strip 400 and the potential
(called Uslave) induced at a
neighbour strip is measured.
The ratio Rsm=Uslave/Vmaster is a
measure of the current leak to
the “slave” strip.
50
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
22
24
Vmaster, V
Four consecutive Vmaster scans from 1 to 23 V were made with the following strips used as the
“slaves”: 399 (immediate neighbour), 427, 371, 399 once more. The master I-V curves show
the PT above ~10 V.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
12
Lancaster, January 2010
B4098: Pth scans with master strip 400 on 29.1.10
For Vmaster ~20V the Uslave is
~1mV i.e. Rsm~5*10-5. that
shows good interstrip
isolation.
1100
399/1
399/2
427
371
1000
900
Uslave, mV
800
700
600
500
400
300
200
0
10
20
30
40
50
Imaster, mA
60
70
80
90
The relation between Uslave
and Imaster is in a good
approximation linear. The
slope is about the same for
low Imaster, dominated by a
current through the bias
resistor, and high Imaster where
the PT dominates. This means
that the PT current doesn’t
leak to the “slave” strip more
than the normal ohmic current.
The Uslave induced on the immediate neighbour strip 399 doesn’t differ from that induced at the
distant strips 427 and 371. This shows that it originates not from the leak between the strips but
from a more general link e.g. via bias rail. The necessary parasitic resistance of ~ Uslave/Imaster is
~10W that is small enough to be plausible.
PTP location studies – AUW 20/04/2010, DESY
A. Chilingarov, A. Weidberg, Bart Hommels
13