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IC History PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory 1947 - Transistor Invented - John Bardeen, Walter Brattain and William Shockley - Shockley founded Shockley Semiconductor - Led to Fairchild Semiconductor 1959 - First Integrated Circuit - Jack Kilby & Robert Noyce • Kilby shares 2000 Noble in Physics IC history cont’d PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory 1965 - Moore’s Law Transistors per IC doubles every 18 months 2300 transistors on the 4004 (‘71) -> 42 Million on the Pentium 4 (’00), 2.3x109 8 core Xenon (11) Shrink Transistor Size by 30% every two years! 1968 - Intel Noyce, Moore, and Grove – All served as CEO Implications of exponentials – Line width PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Actually now closer to 5% From ICKnowledge LLC Shrinking line widths PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Equipment Cost PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Fab Cost PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Die Size PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Pricing PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Still one of the most important industries PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory World Wide Electronics Industry > $1 trillion MOSFET PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory How do we build one of these (let alone millions) on a Chip? For now, let’s look at something easier – Si solar cell PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Starting n-type wafer clean Diffusion doping to form p+ layer pn junction Lithographic Patterning and Etch PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory resist Spin on Photoresist Pattern Resist p n Etch to form mesa isolation PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Etch the Silicon Remove Photoresist p n Oxidize – passivation, electrical isolation PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Oxidation Spin on photoresist Pattern contact layer and etch vias PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Pattern contact fingers Oxide etch Liftoff and Backcontact PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory Evaporate metal “Liftoff” photoresist in solvent Remove back oxide and metallize •Two Levels of Masks - photoresist, alignment •Etch and oxidation to isolate – thermal oxide, deposited oxide, wet etching, dry etching, isolation schemes •Doping - diffusion/ion implantation •Metallization - Materials deposition, PVD, CVD
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