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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999
201
Hybrid Integration of VCSEL’s
to CMOS Integrated Circuits
Rui Pu, Chunjie Duan, and Carl W. Wilmsen, Senior Member, IEEE
Abstract— Three hybrid integration techniques for bonding
vertical-cavity surface-emitting lasers (VCSEL’s) to CMOS integrated circuit chips have been developed and compared in
order to determine the optimum method of fabricating VCSEL
based smart pixels for optical interconnects and free-space optical
processing. Each of the three bonding techniques used different
ways of attaching the VCSEL to the integrated circuit and making
electrical contacts to the n- and p-mirrors. All three techniques
remove the substrate from the VCSEL wafer leaving an array
of individual VCSEL’s bonded to individual pixels. The 4 2 4
and/or 8 2 8 arrays of bonded VCSEL’s produced electrical and
optical characteristics typical of unbonded VCSEL’s. Threshold
voltages down to 1.5 V and dynamic resistance as low as 30 were measured, indicating good electrical contact was obtained.
Optical power as high as 10 mW for a VCSEL with a 20-m
aperture and 0.7 mW with a 6-m aperture were observed. The
VCSEL’s were operated at 200 Mb/s (our equipment limit) with
the rise and fall times of the optical output <1 nS.
Index Terms— Flip-chip bonding, hybrid integration, OEIC,
VCSEL’s.
I. INTRODUCTION
V
ERTICAL-CAVITY surface-emitting lasers (VCSEL’s)
are an ideal light source for free-space optical processing
since they can easily be fabricated into two dimensional arrays
of individually addressed lasers which emit a low divergent
column of light normal to the array surface. However, VCSEL’s do not perform logic or function as switches and thus
must be electrically connected to an electronic processing array
that not only performs the desired function but also provides
the current drive for the VCSEL’s. These processors are called
“smart pixels.” In order to be practical, free space optical
processing requires large arrays of smart pixels that can operate
at high frequency, have uniform performance across the array
and be competitively priced. Reliable foundries are available
to fabricate the complementary metal–oxide–semiconductor
(CMOS) integrated circuits required for the smart pixels
and the fabrication of VCSEL’s has become an established
technology [1]. However, it is a challenging process to integrate a large array of VCSEL’s to a CMOS chip since
the electrical interconnections between the VCSEL’s and the
CMOS electronic driver circuit must be short in order to reduce
the parasitic capacitance, electrical cross talk and the tangle
of interconnect wires that would be required if a separate
VCSEL chip containing a 1000 or more VCSEL’s is located
some distance from the CMOS chip. Thus, the new frontier
for VCSEL’s is the development of reliable techniques for
merging the VCSEL’s with very large, foundry fabricated
smart pixel arrays. Developing this enabling technology will
open up many new applications for VCSEL-based smart pixels
[2]–[4].
This paper reports the successful bonding of arrays of individual VCSEL’s to CMOS integrated circuits, GaAs MESFET
circuits and patterned GaAs substrates using three different
bonding techniques. The characteristics of the three bonding
techniques are discussed and compared. The CMOS/VCSEL
combination is shown to be capable of operating at 500 Mb/s
per channel and have low series resistance.
Previously, other research groups have reported on the
bonding of individual VCSEL’s. Maracas et al. [5] placed
individual VCSEL’s on a silicon chip by attaching the VCSEL
to a probe with water-soluble glue. This approach evolved into
an applique technique [6] similar to that developed by Jokest
and co-workers [7] for photodetectors. This latter technique
fully processes the wafer into VCSEL’s, temporarily attaches
the VCSEL’s to another substrate, removes the substrate from
the VCSEL wafer and then transfers individual VCSEL’s to
the electronic chip. Electrical contracts are then made between
the VCSEL and the electronic chip. Yeh and Smith [8] and
Matsuo et al. [9] have taken the approach of first bonding
the VCSEL wafer to the electronic chip, then removing the
substrate from the VCSEL wafer and processing the remaining
layers into individual VCSEL’s. The Yeh and Smith techniques
attaches the VCSEL wafer to the substrate with a metal
which makes using the VCSEL’s with individual CMOS pixels
difficult. The Matsuo et al. [9] have demonstrate bonding
arrays of VCSEL’s to silicon substrates using polyimide.
We have previously reported using a coplanar bonding
technique [10] to attach 8 8 arrays of individual VCSEL’s
to foundry fabricated GaAs MESFET chips. In this paper we
report using this coplanar process and two other processes to
4 arrays of individual VCSEL’s to CMOS chips
bond 4
and other substrates.
II. VCSEL BONDING TECHNIQUES
Manuscript received November 2, 1998; revised March 8, 1999. This work
was supported by the National Science Foundation under Grant 9408371 and
by Colorado State University under the Program of Research and Scholarly
Excellence.
The authors are with the Department of Electrical Engineering, Colorado
State University, Fort Collins, CO 80523-1373 USA.
Publisher Item Identifier S 1077-260X(99)04791-7.
The research present here was motivated by the need to
develop one or more bonding techniques that are scalable to
1000 VCSELs/cm . The technique(s) must also result in high
performance VCSEL’s that bond reliably without disturbing
the electronic functions of the CMOS chip. Low parasitic
1077–260X/99$10.00  1999 IEEE
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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999
capacitance and low thermal and electrical resistance are also
factors that must be considered. In starting this research, we
first generalized the bonding techniques into three basic types
and then designed, fabricated and tested each of these types. As
part of this process, we decided to concentrate on techniques
that removed the substrate from the VCSEL wafer since this
reduces problems associated with stress induced by multiple
bonds connecting two large chips together, especially since
the two chips are of different material and have different
coefficients of expansion. Removing the substrate also appears
to more readily allow the use of shorter wavelength VCSEL’s.
In addition, we choose to use oxide confined VCSEL’s instead
of either proton implanted, air post or under etched fabrication
techniques, since the oxide confined VCSEL have the highest
efficiency and appeared to be more compatible with the other
processes required for bonding VCSEL’s to CMOS. High
efficiency is also important for large, dense arrays since the
heat generation of the chip set must be limited.
The hybrid integration process includes attaching the VCSEL’s to the electronic pixel chip and making electrical
connection between the VCSEL’s and the electronic circuits
of the pixels.
This paper reports the results of the successful bonding of
the following three hybrid integration techniques.
1) Coplanar Flip-Chip Bonding: With this technique, both
the n- and p-mirror contacts of the VCSEL are bonded to
corresponding metal pads located in the electronic pixel
using a thermo-compression of Au post into InSn solder.
The Au/solder provides both a means of attachment and
electrical connection.
2) Top–Bottom Contact Bonding: This techniques uses a
solder bond to both attach the VCSEL to the electronic
chip and make contact to the p-mirror. The -mirror
contact is made with a deposited thin film.
3) Top Contact Bonding: This technique attaches the VCSEL to the electronic chip with epoxy. Deposited thin
films are used to make both the n- and p-mirror contacts.
4 or
All of the results reported here are for either 4
8 arrays of VCSEL’s bonded on a 250 m pitch. Two
8
30 m bonding pads separated by 25 m on the
30 m
CMOS/substrate were used for all three bonding techniques.
The electronic chips were either: 1) 0.5- m CMOS or 1.0- m
GaAs MESFET technologies which were fabricated through
the MOSIS Foundry Service or 2) specially prepared array patterns on semi-insulating GaAs fabricated in our laboratory. The
VCSEL wafers were grown at Sandia National Laboratories
for an emission wavelength of 850 nm. The VCSEL epitaxial
layers were grown on n-type GaAs wafers in a conventional
way. However, since the bonded VCSEL’s are back emitting,
the light will be emitted through the n-mirror which requires
the n-mirror to be less reflecting than the p-mirror. A 1000A AlAs stop etch layer was grown between the n-mirror and
the substrate. For the present VCSEL wafers, no intercavity
contacting layers were included, although these would reduce
the series resistance of two of the bonding techniques. All
of the VCSEL and bonding processing was performed in our
laboratory except the reactive ion etching, which was done
Fig. 1. Illustration of a coplanar bonded VCSEL to an electronic chip
showing the basic structural features.
Fig. 2. Scanning electron photomicrograph of VCSEL’s coplanar bonded to
a CMOS chip.
either in another laboratory at Colorado State or at Sandia.
The VCSEL’s were fabricated using the oxide confinement
technique with the oxides grown in steam at 430 C. After
bonding the VCSEL’s to the electronic chip, the substrate was
removed from the VCSEL wafer, leaving the -mirror attached
to the electronic chip.
A. The Coplanar Flip-Chip Bonding Technique
This technique takes advantage of the flip-chip bonding
process in which all of the bonds of the VCSEL array are
simultaneously bonded to the bonding pads of the electronic
chip. In order to accomplish this, the VCSEL’s is fully
processed before bonding and the n and p mirror contacts
are formed in such a ways that they are on the same plane,
as illustrated in Fig. 1. After the bonding, the VCSEL wafer
substrate is removed by selective etching, leaving individual
VCSEL’s locally bonded to pads in the smart pixel array as
shown in the scanning electron photomicrograph of Fig. 2.
The oxide confined VCSEL’s were fabricated by dry etching
the device mesa down to the n-mirror which leaves the
wafer surface with 4–5- m steps. While this decreases the
resolution of subsequent photolithography, VCSEL processing
only requires a few micrometer resolution which is readily
obtainable. Furthermore, the coplanar flip chip structure does
PU et al.: HYBRID INTEGRATION OF VCSEL’S TO CMOS INTEGRATED CIRCUITS
203
(a)
Fig. 3. Optical photomicrograph of a 4
bonded to a CMOS chip.
2 4 array of VCSEL’s coplanar
not require a metal aperture (this is the smallest feature of
the VCSEL), thus the resolution requirement is even less
critical. After etching the mesas, wet oxidation is performed.
The p- and n-contacts are then deposited and annealed, and
Au is electroplated on the n-contact to a height level with
the p-contact. The accuracy of the electroplated Au must be
controlled within 0.3 m, otherwise the bonding process has
a low yield. This electroplating is followed by a second plating
of Au posts on both the n- and p-contacts in order to enhance
the bonding. Dry etching down to the substrate then forms
another mesa surrounding this structure.
The bonding pads of foundry fabricated IC’s are Al and
thus will not bond directly to the electroplated Au on the
VCSEL’s. Therefore, Ti–Au–InSn was deposited onto the IC
and patterned to leave this metallization only on the Al pads.
The flip-chip bonding of the VCSEL’s was accomplished by
mounting the VCSEL and electronic chip onto separate glass
plates with crystal bond, aligning them in a mask aligner using
IR and then pressing the two chips together with pressure. If
this part of the process is done properly, then this unit can
be easily transferred to a hot plate and heated to 180 C for
10 min which melts the InSn contacts and bonds the two chips
together. Since the present volume of the InSn is small we
believe that alloying of the InSn with Au occurs, and not
reflow. Further work on the contact metallurgy is required
and increasing the volume of InSn in order to affect reflow
may improve the process.
After the bonding, epoxy is wicked in between the chips to
enhance the robustness of the structure and protect the pixel
chip from attack by the subsequent polish and selective etch
used to remove the GaAs substrate [11], [12]. The epoxy is
then removed with an oxygen plasma leaving free standing
VCSEL’s bonded to the pixels as illustrated in Fig. 3 which
4 array of coplanar
is an optical photomicrograph of a 4
bonded VCSEL’s to a 0.5- m CMOS chip. Nine of the 16
VCSEL’s lased with similar characteristics. We have also
bonded 8 8 VCSEL arrays to GaAs MESFET circuits [10]
and other types of substrates. The light output versus current
( – ) and current versus voltage ( – ) characteristics of five
(b)
Fig. 4. Characteristics for five VCSEL coplanar bonded to the same GaAs
Substrate. (a) L–I curves. (b) I –V curves.
VCSEL’s bonded to a GaAs substrate are given in Fig. 4.
Note that the aperture for this VCSEL is 15 m, which yields
a threshold current, is 3.1 mA, a threshold voltage of 2.8 V,
a dynamic resistance of 30 and a maximum power out of
4 mW. Smaller apertures yield
mA. The VCSEL’s
bonded to CMOS have been driven at 200 Mb/s with rise and
fall times 1 nS, which indicates that the VCSEL/CMOS chip
can operate at 500 Mb/s. Thus, these bonded VCSEL’s have
excellent electrical and optical characteristics. In addition, this
bonding structure is remarkably robust if care is taken not to
forcefully touch the VCSEL’s.
B. Top–Bottom Contacts
The top–bottom contact bonding process is illustrated in
Fig. 5. This process is simpler then coplanar flip chip bonding
since the coplanar electroplating is not necessary and only one
mesa etch is required. The simple square shape of the VCSEL
mesa (as opposed to the rectangular shape of the coplanar
bonding) also makes this structure more robust. Depositing
the p-contacts is the first step in the process followed by
electroplating the Au posts. The VCSEL’s mesas were then
isolated by dry etching below the bottom of the VCSEL’s
and oxidized. The metallizations were carried out before
the etching, because these VCSEL mesas are about 10 m
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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999
Fig. 5. Illustration of a top–bottom bonded VCSEL to an electronic chip
showing the basic structural features of the bonding.
(a)
(b)
Fig. 7. Characteristics for 10 VCSEL’s top–bottom bonded to a GaAs
substrate. (a) L–I curves. (b) I –V curves.
Fig. 6. Scanning electron photomicrograph of VCSEL’s top–bottom bonded
to a patterned GaAs chip.
high which reduces the resolution of the photolithography.
Ti–Pt–Au metallization was used for the p-contact instead
of Ti–Au, since the Pt is needed as a diffusion barrier to
prevent Au diffusing deep into the device during the 430 C
oxidization. The electroplated Au post also protects the ohmic
contact from the corrosive environment of the oxidation step.
Au is deposited onto the Al pads of the CMOS chip and a Au
post electroplated to the approximate height of the VCSEL’s
in order to form part of the top contacts. The height tolerance
of this post is greater than with the coplanar technique.
The bonding and substrate removal process is similar to
that used in the coplanar flip chip, except that the bonding
alignment is not as critical, because there is only one solder bonding pad for each VCSEL. Furthermore, there is no
coplanar accuracy problem. Thus, higher bonding yield can
be expected.
After the substrate is removed, the epoxy covering the Au
post on the electronic chip is oxygen plasma etched away.
Alternately, all of the epoxy can be removed and polyimide
spun on and patterned to provide an insulating planarization
layer. The n-contact metal of the VCSEL’s and the metal
trace between VCSEL n-contact and the Au posts is then
deposited and annealed. Step coverage with this process is not
a serious problem since the epoxy provides a bridge between
the VCSEL and the Au post or the etched contact holes in the
planarizing polyimide provides a smooth transition between
height differences in the electroplating and the top contact.
Increasing the thickness of the metal trace by electroplating
also help the step coverage problem.
The scanning electron photomicrograph of Fig. 6 illustrates
VCSEL’s bonded to a patterned substrate using the top–bottom
technique. Fig. 7 shows 10 – and – curves for VCSEL’s
bonded to a GaAs substrate. These 15- m aperture VCSEL’s
have a threshold current of 2.5 mA, a threshold voltage of 2.6
V, a dynamic resistance of 65 and a maximum power out
of 6 mW.
C. Top-Contact Bonding
With this third technique, the VCSEL wafer is first attached
to the electronic chip with epoxy, the GaAs substrate removed
and the remaining epitaxial layers processed into lasers as
shown in Fig. 8. The epoxy or other nonconductive adhesives
used to attach the wafer must have low shrinkage after curing,
otherwise the very thin epitaxial layers will be distorted by
the bonding material causing breakage, difficulties with photolithography and/or degradation of the VCSEL characteristics.
PU et al.: HYBRID INTEGRATION OF VCSEL’S TO CMOS INTEGRATED CIRCUITS
205
Fig. 8. Illustration of a top-contact bonded VCSEL to an electronic chip showing the basic structural features of the bonding.
(a)
Fig. 9. Scanning electron photomicrograph of VCSEL’s top-contact bonded
to a patterned GaAs chip.
The adhesive used to attach the VCSEL wafer must be able to
withstand the 430 C oxidation temperature. After substrate
removal, the VCSEL processing begins with the deposition
of the n-mirror contacts, followed by dry etching a device
mesa down to the p-mirror. These mesas are shorter than
those in coplanar flip chip structure, because the n-mirror is
thinner than the p-mirror. The p-contacts are then deposited
and isolation mesas were wet etched with the epoxy serving
as the wet etch stop layer. The epoxy not under the mesas is
then removed with an oxygen plasma, which also undercuts
the mesas. After the VCSEL apertures were formed by wet
oxidization, polyimide was spun on and patterned to provide
an insulating layer. Au was then deposited and patterned
into traces that connected the p- and n-contacts to their
corresponding bonding pads on the electronic chip. The Au
trace step coverage is reliable, since the polyimide planarizes
the surface and the side walls of the contact holes in the
polyimide are 45 .
The height and structure of the surface topography of the
epitaxial layer limits the resolution of the photolithography
after it is bonded on the electronic chip. Thus, the more
processing steps carried out after bonding, the worse the
uniformity of the VCSEL characteristics. Since this top-contact
bonding technique has the most process steps after bonding
among these three bonding methods, it will probably have the
most variation in the device characteristics.
(b)
Fig. 10. Characteristics for six VCSEL top contact bonded to a GaAs
substrate. (a) L–I curves. (b) I –V curves.
The SEM photomicrograph of Fig. 9 shows individual VCSEL’s bonded to a specially prepared GaAs substrate using
the top-contact technique. The bonding is seen to be robust
and the alignment of the contacts to have high tolerance. The
– and – characteristics from 6 VCSEL are shown in
Fig. 10, verify that functioning VCSEL’s can be successfully
bonded by this technique. While the power out of from these
VCSEL’s is comparable with that obtained from the other
bonding techniques, the general characteristics are both more
variable and differ from that commonly observed. This, we
believe, is due to the starting VCSEL wafer which had a
different design.
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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999
TABLE I
COMPARISON OF THE IMPORTANT PROCESSING STEPS
FOR THE THREE VCSEL BONDING TECHNIQUES
III. COMPARISON OF THE BONDING TECHNIQUES
The previous section has shown that all three of the techniques produce workable VCSEL arrays bonded to CMOS
and/or other substrates. This section compares the processing
required for each of the techniques and discusses critical
processing steps. The characteristics of each of the bonding
processes are also summarized and discussed.
A. Comparison of the Processing
Each of the bonding techniques requires many processing
steps, the majority of which are routine, e.g., rinsing, plasma
ashing, dry etching, metal deposition, etc. These are common to all three of the techniques and do not provide a
basis for differentiating the difficulty and/or scalability of the
processes. The more critical processing steps and processing
characteristics are listed in Table I. The processing steps that
may limit the scalability of the VCSEL array bonding or
that pose the greatest difficulty to achieving high yield and
high performance have been indicated on the table with an
asterisk. These limiting/critical steps were chosen based on
our experience using our equipment and processing facilities.
Using production type equipment with additional process
controls should mitigate our choice, e.g., we use a mask aligner
to align and perform the initial attachment, while a wafer
bonding machine is much better suited for this task. Some
processing steps, however, are independent of the equipment,
e.g., oxidation after bonding and contact metal deposition. For
this case, the metals on both the IC and VCSEL chips must
be protected from the harsh oxidizing atmosphere. In addition
if polyimide or epoxy is applied before oxidation, then their
properties or mechanical integrity could be compromised.
Table I compares seven different processing parameters.
The number of mask level is often taken as a measure of
the complexity and yield of a process. However, for our
small scale array fabrication, the number of mask levels
did not appear to be a factor, nor is the height of the
surface topography steps for any of the three VCSEL bonding
techniques. The later is due to the low photolithography
resolution required by the processes. The accuracy of the
VCSEL attachment alignment is also not critical since the
30 m) and sufficiently widely
pads are large (30 m
separated (25 m). It is this separation that sets the limit on
the allowable misalignment. The size of the bonding pads and
their separation are not expected to be decrease more that
about a factor of two or three, since the overall size of the
VCSEL’s can not decrease much and the VCSEL/pixel density
will not increase beyond 1000/cm . The heat generated by the
VCSEL will primarily be transmitted to the substrate through
the attachment material. For the coplanar and top–bottom
techniques, the VCSEL attachment is via the metal contacts,
thus the size of the pads may be determined more by the need
to heat sink the VCSEL’s than by the alignment tolerance.
Since the bonded VCSEL arrays become part of an optical
processing/interconnection system, optical alignment must also
be considered. However, bonding arrays as a unit has the
advantage of maintaining the pitch and separation established
by the photomasks used to fabricate the VCSEL’s. This is
independent of the tolerance for bonding to the substrate pads.
Thus alignment of the VCSEL/CMOS chip in the optical
system is the same as required for any array of VCSEL’s.
Exposing the n- and p-mirror contact metallizations to
the 430 C steam used to grow the oxide confinement may
degrade the metal and increase the contact resistance, since the
threshold voltage for the top contact technique is significantly
higher then the other two bonding techniques. However,
with proper design of the metallization, this problem can be
minimized.
The difficult processing steps that may limit the
scaleablity/yield of the VCSEL/CMOS arrays is different
for each of the three techniques. For the coplanar flip chip
bonding, the critical step is the electroplating of the n-mirror
contact to the same level as the p-mirror contact. If the two
contacts are not at the same height, then one of the contact
will not properly bond to the pad on the electronic chip. The
process can be improved by increasing the thickness of the
solder, which can then ball up high enough to connect the
pad and electroplated Au. This will require a larger bonding
pad, which may not be desirable. Further research on the
metallization is required to solve this problem for large arrays.
The top–bottom technique requires connecting the electroplated Au post to the n-mirror contact with a deposited metal
film. This requires using a 10- m-thick polyimide planarization layer on which the thin film is deposited. Therefore, the
polyimide is used to form a smooth transition between the
VCSEL’s and Au posts, otherwise a break in the metal trace
will occur as discussed previously. Increasing the thickness
of the metal trace by electroplating Au has been found to
improve the step coverage.
The top contact technique requires attaching the VCSEL
wafer to the CMOS chip with a nonconductive adhesive such
as epoxy or polyimide. After removal of the VCSEL wafer
substrate and formation of the VCSEL posts by dry etching,
the bonded system, with both VCSEL’s and IC chip, must be
exposed to steam at 430 C for 25 min. Therefore the nonconductive adhesive also protects the bonding pads on the IC
surface. This high temperature processing degrades the epoxy
and may cause the VCSEL’s to detach from the CMOS chip.
No serious problem arose with our 4 4 arrays but finding a
suitable high temperature adhesive may become an issue as the
array size increases. Matsuo et al. [9] used polyimide which
may be the best material for this bonding technique.
PU et al.: HYBRID INTEGRATION OF VCSEL’S TO CMOS INTEGRATED CIRCUITS
TABLE II
COMPARISON OF THE MEASURED ELECTRICAL AND OPTICAL CHARACTERISTICS
OF THE VCSEL’s BOND WITH THE THREE DIFFERENT TECHNIQUES
There are also questions related to the compatibility of
bonding GaAs microchips to silicon CMOS integrated circuits.
Our experience with bonding small arrarys to small chips
indicates that there is no significant difference in bonding
the VCSEL’s to GaAs MESFET chips, CMOS chips and
patterned GaAs substrates. However, differences may surface
when large arrays are bonded to large chips due to differences
in flatness/bowing or thermal expansion. These issues may
also influence the choice of bonding technique and need to be
investigated.
B. Bonded VCSEL Characteristics
As seen above, all three bonding techniques resulted in
working VCSEL’s with reasonable electrical and optical characteristics. This indicates all of these techniques are possible
candidates for large-scale hybrid integration of VCSEL’s.
Electrically, the dynamic resistance and threshold voltage
are the most important parameters in judging the bonding
techniques since they depend on the quality of the contacts.
The threshold current is also important, but it depends on the
mirror reflectivity, material quality and the aperture size. Our
bonded arrays were fabricated from three different wafer and
fabricated at different times and thus had different apertures
and other process variable. In an attempt to obtain a more
meaningful comparison of the after bonding characteristics,
8 arrays at the same time,
we have processed a set of 8
i.e., the arrays were oxidized and metalized at the same time.
The former should result in approximately the same aperture
for all of the VCSEL’s. This appears to be the case since
the threshold current and maximum output power for the
three different bonding techniques are approximately equal.
Unfortunately, the yield for these processing runs were not as
high as the previously obtained due to some small mistakes in
the processing. The electrical/optical characteristic for these
VCSEL’s are shown in Figs. 4, 7, and 10 and summarized
in Table II. At this stage in the development of the bonding
techniques, it is wise not to over analyze the data listed in
this table, however, several observations can be made. First
the resistance of all three techniques is low, in fact the 30
for the coplanar technique is as low as commercial, unbonded
VCSEL’s. The voltage at threshold, however is significantly
of bonded VCSEL’s of previous
higher, although the
processing runs were as low as 1.5 V. In addition, the
of VCSEL’s bonded with the top bonding technique has
consistently been higher than the other two techniques and
has never been lower than 3.4 V. This could be caused by a
lack of intercavity contacting layer in the VCSEL structure.
Since all three techniques yield approximately the same
and power out, one can also conclude that the different
207
processing does not change the basic VCSEL operation or
characteristics. Thus, these parameters do not provide a basis
of selecting the optimum bonding technique.
The thermal resistance and parasitic capacitance of the
bonded VCSEL’s is under investigation. Preliminary data
indicates that the parasitic capacitance is low and that the
thermal resistance is in the same range as unbonded VCSEL
arrays [13], [14]. The mechanical robustness of the bonding
technique is also important but hard to quantify at this time.
Thermal stress and vibration tests will provide some measure
of comparison.
IV. CONCLUSION
We report successfully bonding arrays of individual VCSEL’s to CMOS and other electronic substrates using three
different techniques. The three bonding techniques were sufficiently developed to allow bonding of 4 4 and 8 8 arrays
of VCSEL’s with yields up to 60%. The bonded VCSEL
had electrical and optical characteristics typical of unbonded
VCSEL’s. Threshold voltages down to 1.5 V and dynamic
were measured indicating good
resistance as low as 30
electrical contacts can be obtained. Optical power as high as
10 mW for a VCSEL with a 20 m aperture and 0.7 mW
with a 6- m aperture were observed. In addition VCSEL’s
bonded to CMOS chips were operated at 200 Mb/s with rise
and fall times 1 nS. These results verify that the bonding
processes does not significantly degrade the quality of the
VCSEL’s.
The important process step were summarized and compared
in order to determine which of the step(s) may limit the
scalability and yield of the bonded VCSEL arrays. Control
of the height of the electroplated Au, contact metallization
and step coverage were singled out as steps that may require
further research. Thermal resistance, parasitic capacitance and
mechanical robustness of the bonded VCSEL’s still need to
be investigated in order to complete the evaluation of the
techniques and determine the optimum method of bonding.
ACKNOWLEDGMENT
The authors would like to thank K. Choquette of Sandia
National Laboratories for providing the VCSEL wafers, and K.
Geib of Sandia and A. Goulakov of Colorado State University
for performing dry etching on some of the VCSEL arrays.
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2
2
Rui Pu was born in China. She received the B.S. and M.S. degrees in
electronic engineering in 1992 and 1995, respectively. She is working toward
the Ph.D. degree in oxide-confined VCSEL’s and VCSEL-based smart pixels
at Colorado State University, Fort Collins, CO.
Her M.S. thesis research investigated monolithic integration of distributedfeedback lasers and multiple-quantum-well modulators.
Chunjie Duan was born in Taiyuan, China, in
1970. He received the B.S. degree in electronic
engineering from Tsinghua University, China in
1992 and the M.S. degree in electrical engineering
from Colorado State University, Fort Collins, CO,
in 1998.
For his thesis research, he designed and demonstrated an asynchronous transfer mode optoelectronic switch. Previous to his graduate studies, he
was a systems engineer for Alcatel Bell Telephone
MFG. Co. Presently, he is a hardware engineer for
QUALCOMM Inc.
Carl W. Wilmsen (S’60–M’68–SM’96) received
the Ph.D. degree from the University of Texas at
Austin.
In 1966, he joined the Department of Electrical Engineering at Colorado State University, Fort
Collins, CO. His first 20 years of research were
devoted to the investigation of Josphson tunnelling,
oxide growth on III–V compound semiconductors,
semiconductor surface passivation, and surface analysis using electron spectroscopes. Since that time
his research has concentrated on the development
of optoelectronic switching devices, VCSEL’s and optoelectronic parallel
processing systems. He served as Department Head at Colorado State for seven
years and is presently an Associate Director of the Optoelectronic Computing
System Center.