Download TECHNICAL QUALIFYING EXAMINATION

MASSACHUSETTS INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
TECHNICAL QUALIFYING EXAMINATION
May 27, 2009
Total Points: 100
Time Limit: 120 minutes
YOUR NAME__________________________________________________________
Topic Area: 6.012 – Microelectronic Devices and Circuits
General Instructions:
1. Please do all of your work in the spaces provided in this examination booklet. If you
need additional sheets, be sure to put your name and the name of the examination on
each sheet. Place your answer for each question in the space provided on this booklet.
2. At the end of the examination, please put this booklet and any extra pages you have
used in the envelope provided.
3. Tables of formulas are located at the end of this examination on pages 14- 20.
Special Instructions for 6.012
1. The exam consists of 3 problems on pages 2-13. Please make sure you have all of the
pages. Use the space immediately following each question to show your work and the
answer to the question.
2. All sketches must be adequately labeled
3. You will be graded on both your solution (that is, the work shown) and your final
answer. It is possible to get the right answer, but not receive full credit if your
reasoning is unclear. A few words of explanation are required.
For examiner’s use only:
Satisfactory
______________
Problem 1 (35 points) _____
Marginal
______________
Problem 2 (30 points) _____
Unsatisfactory ______________
Problem 3 (35 points) _____
1
Problem 1. [35 points]
Consider a p+n Si diode with NA = 1018 cm−3 and ND = 1016 cm−3. The electron and hole
diffusion coefficients are 20 cm2/s and 10 cm2/s, respectively. Assume that minority
lifetime of both electrons and holes is 10 ns. Also, assume no recombination effects in the
depletion region and that the quasi-neutral regions (QNR) in the diode are much longer
than the carrier diffusion length (i.e. long diode approximation). The device temperature
is always 300 K and the device area is 10−4 cm2.
a) [4 points] Calculate the built-in voltage of the p+n junction.
b) [6 points] Sketch the change of the total current, Itotal, as well as the electron and hole
currents In and Ip along the diode at a forward bias of 0.5 V (numerical values are not
required).
p+
n
Itotal
In
Ip
x
2
c) [5 points] Calculate the reverse current at a bias of -0.5 V.
d) [4 points] Explain, using physical arguments, why the reverse current in the diode
almost does not change with bias (before breakdown).
3
e) [4 points] Calculate the depletion capacitance of the diode at a bias of 0.5 V.
When the depletion capacitance is measured, its value is twice the expected value. The
reason is an unintentional interfacial dipole between the p+ and n layers.
f) [6 points] Draw the charge distribution, electric field and potential along the diode for
the ideal p+-n junction and for the diode with the unintentional dipole. Assume that the
dipole is formed by negative and positive charges separated by a very small distance,
δ, and that the width of the depletion regions in the p+ and n regions are Wp and Wn,
respectively.
4
g) [6 points] What is the magnitude of the dipole moment? (Hint: The dipole moment is
defined as the magnitude of the product of the positive charge in the dipole and the
distance between positive and negative dipole charges.)
5
Problem 2. [30 points]
Consider an n-MOSFET made from Si doped p-type at NA=1016 cm−3. The source and
drain contacts are ohmic (negligible resistance) and are made from n+-doped regions. The
device is operating at 300 K. The other relevant device parameters are:
Flat-band voltage, VFB = −1.0 V
Source-to-body voltage, VBC= 0 V
Electron mobility, μn = 500 cm2V−1s−1
Hole mobility, μp = 100 cm2V−1s−1
Gate length = 2 μm
Gate width = 20 μm
γ=1 V1/2
Oxide (SiO2) thickness, tox = 10 nm
Oxide charge density, nox= +3×1011cm−2 (located at the Si/SiO2 interface)
Note 1: All the voltages/potentials are referred with respect to the body contact, which is
connected to ground.
Note 2: For simplicity, assume that the electron and hole mobilities are independent of
the charge density.
Note 3: The charge induced in the channel by a given potential, VB, applied at the
Si/SiO2 interface, is given by:
q (V − 2φ
) / KT
QN = −Coxγ ⎛⎜ VB + kT / q ⋅ e B p −Si
− VB ⎞⎟
⎝
⎠
This expression is valid for both weak and strong inversion conditions.
a) [6 Points] Draw the charge distribution and the potential of the structure at the onset
of inversion, when the source and drain contacts are floating (i.e. the transistor
behaves like a simple MOS capacitor.)
6
b) [6 Points] Calculate the threshold voltage of the n-MOSFET.
c) [3 Points] Calculate the channel conductivity near the Si-SiO2 interface under flat
band condition. (Hint: Under flat band condition, you do not have an inverted channel
but you still have mobile charge in the device.)
7
d) [3 Points] Calculate the channel conductivity at the onset of inversion.
e) [6 Points] Estimate the ratio of the electron velocities at the source side and the drain
side of the channel when the gate bias is VT + 0.5 V and VDS = 0.5 V.
8
f) [6 Points] Plot the electron velocity along the channel for the bias conditions
specified in part e).
9
Problem 3. [35 points]
The circuit shown below is a voltage amplifier, where the dimensions of the different
transistors are such that (W/L)1=50/2, (W/L)3=100/2 and (W/L)2B=(W/L)2=(W/L)4=50/4.
We will assume that all backgates are shorted to their respective sources and the
transistors are characterized by the following parameters:
μnCox=50 μA/V2,
γn=γp=1 V-1/2,
Cox=2.3 nF/μm2,
μpCox=25 μA/V2,
λn=λp=-0.05 V-1 @ L=2 μm
Cov=0.5 fF/μm
VTn=-VTp=1 V
a) [5 Points] Calculate VBIAS to assure that all the devices are operating in their
saturation region.
10
b) [8 Points] For the value of VBIAS selected in part (a), draw the small signal
equivalent circuit of the amplifier and calculate the value of all the parameters.
Don’t forget to take into account the parasitic capacitances.
11
c) [5 Points] Calculate the overall DC voltage gain if RS=5 KΩ and RL=500 Ω.
d) [6 Points] Calculate the input and output resistance of the amplifier.
12
e) [5 Points] Find ω3dB for the amplifier.
f) [3 Points] How would you modify the circuit to increase the output resistance of
the amplifier?
g) [3 Points] How would you modify the circuit to increase the frequency response?
13
6.012 Microelectronic Devices and Circuits
TQE, Spring 2009
Parameter Values:
Periodic Table:
q =1.6 × 10 −19 Coul
ε o = 8.854 × 10 −14 F/cm
ε r,Si = 11.7, ε Si ≈ 10 −12 F/cm
ε r , SiO = 3.9, ε SiO ≈ 3.5 × 10 −13 F / cm
2
2
n i [Si @ R.T ] ≈ 10 cm
10
III
IV
V
B
C
N
Al
Ga
Si
Ge
P
As
In
Sn
Sb
−3
kT / q ≈ 0.025V ;(kT / q )ln10 ≈ 0.06V
1μm = 1 × 10 − 4 cm
Electrostatics:
Drift/Diffusion:
Drift velocity :
Conductivity :
Diffusion flux :
Einstein relation :
sx = ±μ m E x
σ = q(μ e n + μ h p)
∂C
Fm = −Dm m
∂x
Dm kT
=
μm
q
The Five Basic Equations:
Electron continuity :
Hole continuity :
Electron current density :
Hole current density :
Poisson's equation :
dE(x)
= ρ (x)
dx
dφ (x)
−
= E(x)
dx
d 2φ (x)
−ε
= ρ (x)
dx 2
ε
E(x) =
1
ε
∫ ρ(x)dx
φ (x) = − ∫ E(x)dx
φ (x) = −
1
ε
∫∫ ρ(x)dxdx
∂n(x,t) 1 ∂J e (x,t)
−
= gL (x,t) − [n(x,t) ⋅ p(x,t) − n i2 ]r(T)
q ∂x
∂t
∂p(x,t) 1 ∂J h (x,t)
+
= gL (x,t) − [n(x,t) ⋅ p(x,t) − n i2 ]r(T)
q ∂x
∂t
∂n(x,t)
J e (x,t) = qμ e n(x,t)E(x,t) + qDe
∂x
∂p(x,t)
J h (x,t) = qμ h p(x,t)E(x,t) − qDh
∂x
∂E(x,t) q
= [p(x,t) − n(x,t) + N d+ (x) − N a− (x)]
∂x
ε
Uniform doping, full ionization, TE
n - type, N d >> N a :
no ≈ N d − N a ≡ N D ,
po = n i2 n o ,
p - type, N a >> N d :
po ≈ N a − N d ≡ N A ,
n o = n i2 po ,
kT N D
ln
q
ni
kT N
φ p = − ln A
q
ni
φn =
14
Uniform optical excitation, uniform doping
n = n o + n'
p = po + p'
Low level injection, n',p' << p o + n o :
n' = p'
dn'
= gl (t) − (po + n o + n')n' r
dt
dn'
n'
+
= gl (t)
dt τ min
with τ min ≈ ( po r)
−1
Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and
low level injection; p-type example):
Minority carrier excess :
Minority carrier current density :
Majority carrier current density :
Electric field :
Majority carrier excess :
d 2 n'(x)
n'(x)
1
−
= −
gL (x)
2
2
Le
De
dx
dn'(t)
J e (x) ≈ qDe
dx
J h (x) = JTot − J e (x)
⎤
1 ⎡
Dh
E x (x) ≈
J e (x)⎥
⎢J h (x) −
qμ h po ⎣
De
⎦
ε dE x (x)
p'(x) ≈ n'(x) +
q dx
Le ≡ De τ e
Short base, infinite lifetime limit:
Minority carrier excess :
d 2 n'(x)
1
1
≈ −
gL (x), n'(x) ≈ −
2
dx
De
De
∫∫ g (x)dxdx
L
Non-uniformly doped semiconductor sample in thermal equilibrium
d 2φ (x)
q
= {n i [e qφ (x ) kT − e−qφ (x ) kT ]− [N d (x) − N a (x)]}
2
ε
dx
n o (x) = n ie qφ (x ) kT , po (x) = n ie−qφ (x ) kT , po (x)n o (x) = n i2
15
Depletion approximation for abrupt p-n junction:
⎧ 0
⎪
⎪−qN Ap
ρ(x) = ⎨
⎪ qN Dn
⎪⎩ 0
for
x < −x p
for −x p < x < 0
for 0 < x < x n
xn < x
for
N Ap x p = N Dn x n
2εSi (φ b − v AB ) (N Ap + N Dn )
q
N Ap N Dn
w(v AB ) =
2q (φ b − v AB )
E pk =
εSi
qDP (v AB ) = −AqN Ap x p (v AB ) = −A 2qεSi (φ b − v AB )
Ideal p-n junction diode i-v relation:
n2
n2
n(-x p ) = i e qv AB / kT , n'(-x p ) = i (e qv AB / kT −1);
N Ap
N Ap
iD
⎡ D
De ⎤ qv AB / kT
h
= Aq n ⎢
+
-1]
⎥ [e
⎣ N Dn w n,eff N Ap w p,eff ⎦
2
i
-x p
qQNR,p -side = Aq
∫ n'(x)dx,
kT N Dn N Ap
ln
n i2
q
φb ≡ φn − φ p =
p(x n ) =
w m,eff
wn
qQNR,n -side = Aq ∫ p'(x)dx,
-w p
⎧
⎪
= ⎨
⎪
⎩
N Ap N Dn
(N
Ap
+ N Dn )
N Ap N Dn
(N
Ap
+ N Dn )
n i2 qvAB / kT
n2
e
, p'(x n ) = i (e qv AB / kT −1)
N Dn
N Dn
if L m >> w m
wm − x m
Lm tanh [(w m − x m ) Lm ] if L m ~ w m
Lm
if L m << w m
Note : p'(x) ≈ n'(x) in QNRs
xn
Ebers-Moll Model for Bipolar Junction Transistor (BJT) Characteristics:
(npn; no base width modulation)
iE (v BE ,v BC ) = − IES (e qvBE / kT −1) + α R ICS (e qvBC / kT −1)
iC (v BE ,v BC ) = α F IES (e qvBE / kT −1) − ICS (e qvBC / kT −1)
with :
⎛ D
⎛ D
De ⎞
De ⎞
h
h
IES ≡ Aqn i2 ⎜⎜
+
+
⎟⎟, ICS ≡ Aqn i2 ⎜⎜
⎟⎟,
⎝ N DE w E ,eff N AB w B,eff ⎠
⎝ N DC wC ,eff N AB w B,eff ⎠
αF ≡
(1− δB ) , α ≡ (1− δB ) , δ
(1+ δE ) R (1+ δC ) E
≡
w2
w
Dh N AB w B ,eff
D N
⋅
⋅
, δB ≡ B,eff
, δC ≡ h ⋅ AB ⋅ B ,eff
2
De N DE w E ,eff
2Le
De N DC wC ,eff
Large signal BJT Model in Forward Active Region (FAR):
(npn with base width modulation)
iB (v BE ,vCE ) = IBS (e qvBE / kT −1)
iC (v BE ,v BC ) = β F iB (v BE ,vCE )[1+ λvCE ] = β F IBS (e qv BE / kT −1)[1+ λvCE ]
with :
IBS ≡
IES
Aqn i2 ⎛ Dh
De ⎞
=
+
⎜⎜
⎟,
(β F + 1) (β F + 1) ⎝ N DE wE ,eff N AB wB,eff ⎟⎠
βF ≡
αF
, and
(1− α F )
λ≡
1
VA
16
MOS Capacitor:
Flat - band voltage : VFB ≡ vGB at which φ (0) = φ p−Si
VFB = φ p−Si − φ m
Threshold voltage : VFB ≡ vGC at which φ (0) = − φ p−Si + v BC
VT (v BC ) = VFB − 2φ p−Si +
{
[
1
2εSi qN A 2φ p−Si − v BC
*
Cox
x DT (v BC ) =
Depletion region width at threshold :
*
Cox
=
Oxide capacitance per unit area :
]}
1/ 2
[
2εSi 2φ p−Si − v BC
]
qN A
εox
[ε
t ox
r,SiO2
= 3.9,
εSiO ≈ 3.5x10−13 F /cm]
2
*
q*N = −Cox
[vGC − VT (v BC )]
Inversion layer sheet charge density :
Accumulation layer sheet charge density :
*
q*P = −Cox
[vGB − VFB )]
Gradual Channel Appoximation for MOSFET Characteristics:
(n-channel; no channel length modulation)
with VT (v BS ) ≡ VFB − 2φ p−Si +
W
*
K ≡ μe Cox
,
L
{
[
1
2εSiqN A 2φ p−Si − v BS
*
Cox
*
Cox
≡
εox
t ox
,
]} ,
1/ 2
⎧
1 ⎪
εSiqN A
α ≡ 1+ * ⎨
Cox ⎪ 2 2φ p−Si − v BS
⎩
[
Good only for v BS ≤ 0, and v DS ≥ 0 :
iG (vGS ,v DS ,v BS )
⎧
0
for
⎪
⎪⎪
K
2
iD (vGS ,v DS ,v BS ) = ⎨
for
[vGS − VT (v BS )]
2α
⎪
⎪ K ⎧⎨v − V (v ) − α v DS ⎫⎬ v
for
T
BS
DS
⎪⎩ ⎩ GS
2 ⎭
= 0,
1
α
1/ 2
⎫
⎪
⎬
⎪⎭
]
iB (vGS ,v DS ,v BS ) = 0
[vGS − VT (v BS )] < 0 < v DS
0<
1
α
[vGS − VT (v BS )] < v DS
0 < v DS <
1
α
[vGS − VT (v BS )]
Note: α is typically assumed to be equal to 1 (i.e. α=1) unless otherwise stated. Large Signal MOSFET Model in Saturation (FAR):
(n-channel with channel length modulation)
1
When v BS ≤ 0, vGS ≥ VT (v BS ), and v DS ≥ [vGS − VT (v BS )] :
α
iG (vGS ,v DS ,v BS ) = 0,
iB (vGS ,v DS ,v BS ) = 0
K
2
iD (vGS ,v DS ,v BS ) =
[vGS − VT (v BS )] [1+ λ(v DS − v DS,sat )]
2α
with λ ≡
1
VA
17
Small Signal Linear Equivalent Circuits:
•
p-n Diode (n+-p doping assumed for Cd)
gd ≡
∂iD
∂v AB
=
Q
q
q ID
IS e qVAB / kT ≈
,
kT
kT
Cd = Cdp + Cdf ,
qεSi N Ap
where Cdp (VAB ) = A
,
2 (φ b − VAB )
•
BJT (in FAR)
q
gm =
β o IBS e qVBE
kT
go = β o IBS [e qVBE
kT
kT
[1+ λVCE ]
≈
+ 1] λ ≈ λ IC
q I [w p − x p ]
and Cdf (VAB ) = D
= gd τ d
kT
2De
2
q IC
,
kT
⎛
IC ⎞
⎜ or ≈
⎟
VA ⎠
⎝
Cπ = gm τ b + B-E depletion cap. with τ b ≡
•
gπ =
w B2
,
2De
gm
βo
=
with τ d
[w
≡
− xp]
2
p
2De
q IC
β o kT
Cμ : B-C depletion cap.
MOSFET (in saturation)
gm = K [VGS − VT (VBS )][1+ λVDS ] ≈ K [VGS − VT (VBS )] =
go =
K
2
[VGS − VT (VBS )] λ ≈ λ ID
2
gmb = η gm = η 2K ID
2K ID = 2ID [VGS − VT (VBS )]
⎛
ID ⎞
⎜ or ≈
⎟
VA ⎠
⎝
with η ≡ −
∂VT
∂v BS
=
Q
1
*
Cox
εSiqN A
qφ p − VBS
2
*
Cgs = W L Cox
,
Csb ,Cgb ,Cdb : depletion capacitances
3
*
*
, where Cgd
is the G-D fringing and overlap capacitance per unit gate length (parasitic)
Cgd = W Cgd
18
Single transistor analog circuit building block stages
BIPOLAR
Voltage
Current
Input
Output
gain, Av
gain, Ai
β gl
−
[g o + g l ]
resistance, Ri
resistance, Ro
⎛ 1 ⎞
⎟⎟
ro ⎜⎜ =
⎝ go ⎠
(
)
gm
≈ − g m rl'
[g o + g l ]
gm
≈ g m rl'
Common base
[g o + g l ]
[g m + g π ] ≈ 1
Emitter follower
[g m + g π + g o + g l ]
r
≈− l
Emitter degeneracy
RF
[g − G F ] ≈ − g R
− m
Shunt feedback
m F
[g o + G F ]
Common emitter
−
(
MOSFET
Common source
Common gate
−
)
rπ
≈1
β gl
≈
[g o + g l ]
rπ + [β + 1]rl'
≈β
≈β
−
≈ [β + 1]ro
rπ
[β + 1]
gl
GF
≈
R
1
+ S
β
gm
≈ rπ + [β + 1]R F
≈ ro
1
⎛
⎞
1
⎟⎟
ro || R F ⎜⎜ =
+
g
G
o
F ⎠
⎝
g π + G F [1 − Av ]
Voltage
Current
Input
Output
gain, Av
gain, Ai
resistance, Ri
∞
∞
resistance, Ro
⎛ 1 ⎞
⎟⎟
ro ⎜⎜ =
⎝ go ⎠
⎧ [g + g mb + g o ]⎫
≈ ro ⎨1 + m
⎬
gt
⎭
⎩
1
1
≈
[g m + go + gl ] g m
(
gm
= − g m rl'
[go + gl ]
)
≈ [g m + g mb ]rl'
≈1
gm
≈1
[g m + g o + gl ]
Source degeneracy
r
≈− l
(series feedback)
RF
[g − GF ] ≈ − g R
Shunt feedback
− m
m F
[g o + GF ]
Source follower
−
1
[g m + g mb ]
≈
∞
∞
∞
∞
≈ ro
gl
GF
1
GF [1 − Av ]
⎞
⎛
1
⎟⎟
ro || RF ⎜⎜ =
⎝ [g o + GF ] ⎠
OCTC/SCTC Methods for Estimating Amplifier Bandwidth
-1
OCTC estimation of ω HI:
ω HI
-1
⎡
⎤
⎡
⎤
−1
≤ ⎢∑ [ω i ] ⎥ = ⎢∑ RiCi ⎥
⎣ i
⎦
⎣ i
⎦
with Ri defined as the equivalent resistance in parallel with Ci with all other
parasitic device capacitors (Cπ's, Cµ's, Cgs's, Cgd's, etc.) open circuited.
SCTC estimation of ω LO:
ω LO ≥
∑ω = ∑ [R C ]
−1
j
j
j
j
j
19
with Rj defined as the equivalent resistance in parallel with Cj with all other
baising and coupling capacitors (CΙ's, CO's, CE's, CS's, etc.) short circuited.
Difference- and Common-mode signals
Given two signals, v1 and v2, we can decompose them into two new signals, one
(vC) that is common to both v1 and v2, and the other (vD) that makes an equal, but
opposite polarity contribution to v1 and v2:
v D ≡ v1 − v 2
and
vC ≡
[v1 + v 2 ]
⎯
⎯→
2
v1 = vC +
vD
2
and
v1 = vC −
vD
2
CMOS Performance
Transfer characteristic:
In general : VLO = 0,
VLO = VDD ,
ION = 0,
IOFF = 0
V
Symmetry : VM = DD and NM LO = NM HI ⇒ K n = K p and VTp = VTn
2
Minimum size gate : Ln = L p = Lmin , W n = W min , W p = (μn μ p )W n
Switching times and gate delay:
τ Ch arg e = τ Disch arg e =
2CLVDD
2
K n [VDD − VTn ]
*
*
CL = n(W n Ln + W p L p )Cox
= 3nW min Lmin Cox
τ Min.Cycle = τ Ch arg e + τ Disch arg e =
assumes μe = 2μh
12nL2minVDD
2
μe [VDD − VTn ]
Power dissipation:
Pave @ Max. f = CLV
2
DD
f max ∝
2
CLVDD
τ Min.Cycle
μeW minεoxVDD [VDD − VTn ]
2
∝
t ox Lmin
Pave@Max. f
P
μ ε V [V − VTn ]
=
∝ ave@Max. f ∝ e ox DD 2DD
InverterArea W min Lmin
t ox Lmin
2
PDave @ Max. f
Device transit times:
Short Base Diode transit time : τ b =
w B2
w B2
=
2Dmin,B 2μmin,BVthermal
Channel transit time w.o. velocity saturation : τ Ch
L2
2
=
3 μCh VGS − VT
Channel transit time with velocity saturation : τ Ch =
L
ssat
20