Download EE 5342 Lecture

Semiconductor Device
Modeling and Characterization
EE5342, Lecture 26
Spring 2003
Professor Ronald L. Carter
[email protected]
http://www.uta.edu/ronc/
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1
n-channel enhancement
MOSFET in ohmic region
Channel
VS = 0
0< VT< VG
EOx,x> 0
n+ +e+-e+ -+ e+ -+ +e+- + +e+- +
Depl Reg
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p-substrate
VB < 0
e- channel ele
+ implant ion
0< VD< VDS,sat
n+
Acceptors
2
Fully biased nchannel VT calc
p  substrate : VG, at threshold  VT
VT  Vs  VFB  2p 
Q'd,max
 VFB  V
C'Ox
 ni 
p  Vt ln   0, Q'd,max  qNa xd,max ,
 Na 
xd,max 
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

2 2 p  VB  Vs 
qNa
, V  0
3
Values for ms
with silicon gate
n

poly to p - Si : ms

 NCNa  
 Si   Si  Vt ln 2  
 ni  

 NCNa  Eg
 Na 
Note : Vt ln 2    Vt ln 
 ni 
 ni  2q
Eg 
 NC  

p poly to n - Si : ms  Si    Si  Vt ln  
q 
 Nd  
 NC  Eg
 Nd 
Note : Vt ln    Vt ln 
 ni 
 Nd  2q
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Fig 8.11**
|Q’d,max|/q (cm-2)
xd,max (microns)
Q’d,max and xd,max for
biased MOS capacitor
5
I-V relation
forn-MOS
C'


W
2
ID 
2VG  VT VDS  VDS
. Note for
2
L
ohmic
VDS  VG  VT  VDS,sat ,
ID
non-physical
result is non - physical.
ID,sat
At VDS,sat , n's,y L  0
n Ox
assume that channel curr.
is const for VDS  VDS,sat
ID,sat
nC'Ox W
VGS  VT 2

2
L
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saturated
VDS,sat
VDS
6
MOSFET equivalent
circuit elements
Fig 10.51*
Cgs
2
1
 COx , Cgd  COx , COx  WLC'Ox
3
3
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MOS small-signal
equivalent circuit
Fig 10.52*
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MOS channellength modulation
Fig 11.5*
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Analysis of channel
length modulation
Assume the DR change  the channel
L
length modulation, so I'D 
ID
L  L
2Si
L 
2 p  VDS,sat  VDS
qNa


 2 p  VDS,sat , VDS  VDS  VDS,sat
 ID,sat
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n C'Ox W
VGS  VT 2 1  VDS 

2 L
10
Channel length modulated drain char
Fig 11.6*
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Associating the
output conductance
nC'Ox W
VGS  VT 2 1  VDS 
ID,sat 
L
2
ID
ID
gd 
ID,sat
VDS V
slope 
GS
ID,sat
gds,sat

gds,sat 
1  VDS 
 ID,sat
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VDS,sat
VDS
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SPICE mosfet Model
Instance
CARM*, Ch. 4, p. 290
M
MOSFET
General Form
M<nam e> < drain node> <gate node> < source node>
+ <bulk /subs trate node> <model nam e>
+ [L=< value>] [W=< value> ]
L = Ch. L. [m]
+ [AD= <value>] [AS= <value>]
W = Ch. W. [m]
+ [PD= <value>] [PS= <value>]
+ [NRD=< value>] [NRS=<value>] AD = Drain A [m2]
+ [NRG=<v alue>] [NRB= <value>] AS = Source A[m2]
+ [M= <value>]
Examples
NRD, NRS = D and
S diff in squares
M1 14 2 13 0 PNOM
L=25u W=12u
M13 15 3 0 0 PSTRONG
M = device multiplier
M16 17 3 0 0 PSTRONG M=2
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M28 0 2 100 100 NWEAK L=33u W=12u
SPICE mosfet
model levels
• Level 1 is the Schichman-Hodges
model
• Level 2 is a geometry-based,
analytical model
• Level 3 is a semi-empirical, shortchannel model
• Level 4 is the BSIM1 model
• Level 5 is the BSIM2 model, etc.
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SPICE Parameters
Level 1 - 3 (Static)
Param. Parameter Description
Def.
Typ.
Units
1
1
V
VTO
Zero-bias Vthresh
KP
Transconductance
GAMMA
Body-effect par.
0.0
0.35
V^1/2
PHI
Surface inversion pot.
0.6
0.65
V
0.0
0.02
1/V
LAMBDA Channel-length mod.
2.E-05 3.E-05
A/V^2
TOX
Thin oxide thickness
NSUB
Substrate doping
0.0
1.E+15
cm^-3
NSS
Surface state density
0.0
1.E+10
cm^-2
LD
Lateral diffusion
0.0
8.E-05
m
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1.E-07 1.E-07
m
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SPICE Parameters
Level 1 - 3 (Static)
Param. Parameter Description
Def.
Typ.
1
1
600
700
Units
TPG
Type of gate material*
UO
Surface mobility
IS
Bulk jctn. sat. curr.
JS
Bulk jctn. sat. curr. dens.
PB
Bulk junction potential
0.8
0.75
V
RD
Drain ohmic resistance
0
10
Ohms
RS
Source ohmic resistance
0
10
Ohms
RSH
S/D sheet ohmic res.
0
10
Ohms/sq
1.E-14 1.E-15
cm^2/V-s
A
A/m^2
* 0 = aluminum gate, 1 = silicon gate opposite substrate type,
2 = silicon gate same as substrate.
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SPICE Parameters
Level 1 - 3 (Q & N)
Param. Parameter Description
Def.
Typ.
Units
0
1.E-09
Fd/m^2
CJ
Zero-bias bulk cap./A
MJ
Bulk jctn. grading coeff.
0.5
0.5
CJSW
Zero-bias perimeter C/l
0
1.E-09
MJSW
Per. C grading coeff.
0.5
0.5
FC
For.-bias cap. coeff.
0.5
0.5
CGBO
Gate-bulk overlap C/L
0
2.E-10
Fd/m
CGDO
Gate-drain overlap C/L
0
4.E-11
Fd/m
CGSO
G-S overlap C/L
0
4.E-11
Fd/m
AF
Flicker-noise exp.
1
1.2
KF
Flicker-noise coeff.
0.0
1.E-26
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Fd/m
17
Level 1 Static Const.
For Device Equations
Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni)
- q*NSS*TOX/eOx
VTO = as given, or
= Vfb + PHI + GAMMA*sqrt(PHI)
KP = as given, or
= UO*eOx/TOX
CAPS are spice pars., technological
constants are lower case
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Level 1 Static Const.
For Device Equations
b = KP*[W/(L-2*LD)] = 2*K, K not spice
GAMMA = as given, or
= TOX*sqrt(2*eSi*q*NSUB)/eOx
2*phiP = PHI = as given, or
= 2*Vt*ln(NSUB/ni)
ISD = as given, or = JS*AD
ISS = as given, or = JS*AS
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Level 1 Static
Device Equations
vgs < VTH, ids = 0
VTH < vds + VTH < vgs,
id = KP/2*[W/(L-2*LD)]*[vgs-VTH-vds/2]
*vds*(1 + LAMBDA*vds)
VTH < vgs < vds + VTH,
id = KP*[W/(L-2*LD)]*(vgs - VTH)^2
*(1 + LAMBDA*vds)
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References
• CARM = Circuit Analysis Reference Manual,
MicroSim Corporation, Irvine, CA, 1995.
• M&A = Semiconductor Device Modeling with
SPICE, 2nd ed., by Paolo Antognetti and Giuseppe
Massobrio, McGraw-Hill, New York, 1993.
• M&K = Device Electronics for Integrated Circuits,
2nd ed., by Richard S. Muller and Theodore I.
Kamins, John Wiley and Sons, New York, 1986.
• Semiconductor Physics and Devices, by Donald A.
Neamen, Irwin, Chicago, 1997
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