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Encryption Transaction with
3DES
Objective: To implement a
secure credit card transaction
using 3DES encryption using
Kerberos-style authentication.
Team W2
Yervant Dermenjian
Taewan Kim
Evan Mengstab
Xiaochun Zhu
(W21)
(W22)
(W23)
(W24)
Design Manager: Rebecca Miller
Current Stage: Short Final Presentation 04/12/2004
Status Update
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Have not found source of voltage drop on Vdd problem
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Debugging Attempts
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1) Simulate PC alone with long Vdd & Gnd rails: Works
2) Simulate (1) with min sized buffers on input AND output: Works
3) Simulate PCROM alone with long Vdd & Gnd rails: Works
4) Simulate (3) with min sized buffers on input AND output: Works
5) Simulate PC & PCROM together without resistances: Works
6) Simulate PC & PCROM together with resistances: Doesn't Work
7) Remove excess M1 to Gnd contacts in ROM and decoder in (6):
Doesn't Work
8) Do (7) with NWell and contacts along long Vdd rail: Works
They’re connected by a few microns of wire: Shouldn’t be a problem
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Workaround: Layed Vdd and Gnd rails everywhere possible
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Runs at 150MHz
Project Description
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Implement Triple DES Encryption using 0.18μ CMOS
technology
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Attain speeds appropriate for application in
Automated Teller Machines (200MHz)
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Integrate Encryption into ATM transation
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Use Kerberos-style authentication
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Encrypt User Information as data using CC# and Pin
as Keys
Transaction Authorizer decrypts using CC# and Pin
(which they know)
Credit Card Number and PIN are never transmitted,
but are essential to authenticate
Marketability
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Point-of-sale terminals transmit your name, credit card
number, and expiration dates ‘in the clear.’
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Credit and charge card fraud costs cardholders and
issuers hundreds of millions of dollars each year
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Using Kerberos-style authentication, we transmit
encrypted information that can be verified by the card
authorizer without actually containing sensitive
information.
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Uses existing cards and phone network
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Finalist for the 2001 Advanced Encryption Standard
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April 1, 2005 – MasterCard requires all ATMs be
3DES compliant
System Integration
Triple DES Compliant
Unencrypted
Card# + PIN
Verified
Verified
Triple DES
Encryption
Encrypted Card# + PIN
Encrypted Card# + PIN
The 3DES Algorithm
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Overview
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DES vs. 3DES
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Block Cipher - acts on a 64-bit block of plaintext
Converts it into a 64-bit block of cipher text using a 56-bit
key
Specified in FIPS Pub 46-3
Symmetric Key Cipher – encryption & decryption use
same key
3DES applies 3 stages of DES with a separate key for
each stage
Total key length in 3DES is 56 bits x 3 key = 168 bits
Stages
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Stage 1: Encrypt plaintext with Key 1
Stage 2: Decrypt cipher text from Stage 1 with Key 2
(produces new cipher text)
Stage 2: Encrypt cipher text from Stage 2 with Key 3
3DES Algorithm Flowchart (I)
Encryption
DES-1
DES
K1
K2
K3
DES-1
DES
DES
Plain Text
Decryption
DES-1
Cipher Text
3DES Algorithm Flowchart (II)
Extension
32 bit 48 bit
Left Half
Sub
key
64 bit plain Text
Initial Permutation
48 Bit XOR
S Box
16 Rounds
Encryption
32 Bit XOR
Final Permutation
Single
Round
Right Half
cipher Text
3DES Algorithm Flowchart (III)
Key Schedule
56bit Key
Initial Permutation
I=1
I=I+1
Left/Right Half 28 bits
Left Barrel Shift
N
I=16?
Final Permutation
Y
Ready
48 bit Sub-key [ I ]
Density
.09 Trans/um2
=
clock
Enc_ShiftL
Dec_ShiftL
Input
125,534 um2
.126 mm2
All large functional blocks use Metal 1 269
andum
Metal 2.
334.37 um Program Control
32’b XOR
56’b 2:1 mux
32’b 2:1 mux
PC-2 wiring
(L)56b -> 48b
32’b Text Register
IP-1
IP Wiring
PC-2 wiring 56b -> 48b
Mux 56’b 2:1 mux
Mux
KeySub 56’b-1Register
Enc_ShiftL
Des_ShiftR
KeySub
mux
2:1 Register
IP 56’b56’b
56’b 2:1 mux
56’b Key Latch
64 -> 56
Output
Expand
S-box 512 x 4’b
Expand
32’b Text Register (R)
32’b Mux
32’b Mux
48’b XOR
32’b XOR
IP-1 Wiring
415 um
XOR
Reg
64’b
Text 32’b
P Wiring
mux
64’b 2:1
x 4’b
512
S-box
IP (wiring)
48’b XOR
32’b 2:1 demux
Expand
32’b 2:1 mux
32’b 2:1 mux
Data Reg (R) 32’b
(Instruction ROM)
Mux
56’b
Left Barrel Shifter
2:1 demux
64’b
Right Barrel Shifter 56’b
56’b Key Reg
32’b 2:1 demux
64 ->2:1
56 demux
PC (wiring) 64’b
Program Control
IP (wiring)
56’b Key Latch
(Instruction ROM) PC2
64’b 2:1 mux
PC (wiring)
56’b 2:1 mux
Data Reg (L) 32’b
PC1
Input
32’b Latch
Input
Program Control
32’b Latch
Output
Total Area:
111947 um2
2
377.44
um
= 0.112mm
P Wiring
367μm
64’b
P
48’b XOR
Revised
Floorplan
Final Floorplan
Original
Floorplan
M1
M2
M3
M4
Output
2:1 mux
Transistor
Density: 0.136
trans/ um2
379μm
Expected Output :
Verification 2f 81 a8 bf 3c 6b df b4
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Verify
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C Simulation
Behavioral
Schematic
Layout
C code Verification
Structural Verification
Behavioral Verification
Spice Verification
Problems Encountered
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Layout
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Interconnections between components back and forth due
to complicated algorithm
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Permutations take too much space
Spice Simulation
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Vdd Strength drops along conductor wires
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No DC path to ground from node
Module Specifications
BlockName
32'b Latch
56'b Mux
56'b Left Barrel Shifter
56'b Right Barrel Shifter
56'b Key Register
32'b Mux
32'b XOR
48'b XOR
Expand Permutation
Control Logic Buffers
64'b Text Register
64'b Mux
SBOX (each)
Inverse IP Permutation
IP Permutation
PC2 Permutation
P Permutation
PCROM
Program Counter (PC)
PC1 Permutation
Transistors
512
336
392
392
1344
192
256
384
160
36
1536
384
592
256
256
192
128
798
186
240
Area
2129.76
2265.554
3696.1
3696.1
6818.04
1297.628
1687.284
2526.336
3621.4479
239.512
7864.5672
2606.9526
2357.343
16609.0176
16609.0176
5815.4391
6410.331
2593.08
1201.2831
10824.0363
Density
(tr/um^2)
0.240402674
0.148308096
0.106057737
0.106057737
0.1971241
0.147962282
0.151723124
0.151998784
0.044181224
0.150305621
0.195306361
0.14729842
0.251130192
0.015413314
0.015413314
0.033015564
0.019967768
0.307742144
0.154834443
0.022172875
Overall Chip Specifications
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Input Pins
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Output Pins
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32 Data Pins (used for input text and keys)
1 Clock Pin
1 Reset Pin (asserted high)
1 Vdd Pin
1 Ground Pin
32 Cipher Text Pins (64’b cipher text delivered over 2 clocks)
1 Valid Output Pin
1 Get Next Key Pin
Total Pin Count: 70
Chip Aspect Ratio: 1.03
Chip Area: 139093 μm2 = 0.139093 mm2
Total Transistor Count: 13,697 (PMOS: 4,324 NMOS: 9,373)
Transistor Density: 0.09847 transistors/μm2 = 10.155 μm2/transistor
Operation: 256’b Input
64’b Output over 54 clock cycles
Faster Clock Speed: 150MHz
Total Throughput: 169.54 Mbits / second
Layer Masks
Control
Program
XOR
S BOX ROM and Decoders
P Permutation
Expand Permutation
Text Register
Final Permutation
Initial Permutation
Key Register
PC2 Perumtation
Barrel Shifting
Initial Permutation
Input Latch
Full Chip Layout
Final Presentation Breakdown
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Marketing
Algorithm Description
Design Process
Floorplan Evolution
Verification
Issues
Specifications
Layout
Conclusions
Evan
Xiaochun
Evan
Taewan
Taewan
Yervant
Xiaochun
Yervant
Yervant