Download For PowerPAC

In-System Programmable
PROGRAMMABLE ANALOG CIRCUITS
ispPAC™
PowerPAC1208
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Agenda
• What is PowerPAC
• Details of PowerPAC
• Application Example
• PAC-Designer 1.9.1 – Demonstration
• Summary
© LATTICE SEMICONDUCTOR CORPORATION 2002
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What is PowerPAC?
ispPAC-POWR1208-01T44I
Single Chip, In-System Programmable
Power Sequencing & Monitoring Solution
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Where Does PowerPAC Fit On a Board?
3.3V
Board Power
Supply
3.3V
Section
2.5V
Multi-Supply
Circuit Board
Sequenced 3.3 V Bus
3.3 V Input
1.8V
LDO/
Brick
Supply
Supply
Brick
2.5V
Sequenced 2.5 V Bus
FET/ LDO/Brick
Enable
Monitor
Voltages
© LATTICE SEMICONDUCTOR CORPORATION 2002
1.8V Bus
PowerPAC
4
Supervisory
Signals
PowerPAC1208 Block Diagram
Vdd = 2.25V to 5.5V
Monitors Supply
Voltages
PowerPAC
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
8
Analog
Inputs
12
Sequence
Controller
CPLD
Monitors
Digital
Signals
32 I/P & 16
Macrocell
GLB
Digital
Inputs
250kHz
Internal
OSC
4
Logic
Outputs
4 Timers
External Clock for
Longer Time Delay
OUT5
OUT6
OUT7
OUT8
FET Gate
Drive /
Supervisory
Signal
Supervisory
Signals
CLKIO
JTAG
44-Pin TQFP
© LATTICE SEMICONDUCTOR CORPORATION 2002
High Voltage
Outputs
VDD
HVOUT1
HVOUT2
HVOUT3
HVOUT4
4
5
IN1
IN2
IN3
IN4
Comparator
Outputs
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
Comparator
Outputs for
External
Logic
Expansion
& Control
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PowerPAC’s Ruggedized Operation
• Reliable Operation During Rough Power Supply Conditions
–
–
–
–
–
Fast Rise
Slow Ramp
Non-Monotonic Ramp
Sudden Dips in Supply Voltages
Supply Voltage Range of Operation– 2.25V to 5.5V
 All DC and AC Parameters are Specified Down to 2.25V
 All Outputs Operate down to 1.9V Supply
• Input Glitch Immunity up to 20 s
• Industrial Temperature Range
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Features of PowerPAC1208
Analog Section:
• 12 Comparators – To Monitor Power Supply Voltages
– Individual Programmable Threshold
 1% Threshold Resolution around 6 popular Power Supply Voltages
 192 Steps
– Input Hysteresis Auto-Scales With Monitor Voltage
 Maintains Noise Tolerance Across Supply Voltages
– Programmable Input Glitch Filter
• 4 FET Drivers – To Enable/Sequence Power Supply Bus
– Power Supply Ramp Rate - Controlled To Meet Device Specifications
 Programmable Output Current Feed – 500 nA to 50 uA – 32 steps
– Internally Charge Pumped – To Reduce MOSFET On-Resistance
 Configurable High Voltage for FET Driver – 8V to 12.5V – 8 Steps
 To Meet Gate Voltages for Different Power Supplies
– Configurable as Open Drain Output - For Digital Control
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PowerPAC1208 Programmable Delays
3.3V Supply
2.5V Supply
2ms
4ms
16ms Delay
8ms
Composite Plot Showing 6 Different Delay Settings for the 2.5V
Control Signal.
© LATTICE SEMICONDUCTOR CORPORATION 2002
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PowerPAC1208 Slew Rate Control
Select Output Mode
3.3V Supply
2.5V Supply
Composite Plot Using Different Ramp Currents for the 2.5V
HVOUT Signal.
© LATTICE SEMICONDUCTOR CORPORATION 2002
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FET Driver Ramp Current
and Max Voltage
Features of PowerPAC1208 – Cont’d
Digital Section:
• 16 Macrocell CPLD (Similar to ispMACH4000 Macrocell)
– Supports Supply Sequencing & Supervisory Signal Generation
– Ruggedized to Operate Reliably Under Noisy Environments
– 32 Input, 80 Product Term
• 250 kHz Oscillator – Flexible Timing Generation
– Pre-scalar for Slower PLD Operation Down to 2 kHz Clock
• 4 Programmable Timers
– Programmable Duration –Implements Delays for Power Supply
Stabilization, Watchdog Timers, etc.
 32 us to 512 ms with Internal Oscillator – 16 Steps
 Extend Timer Duration to Any Length Using External Clock
– Controlled by Macrocell Output – Reuse the Same Timer Under
Different Logic Conditions
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Features of PowerPAC1208 – Cont’d
• 4 Digital Inputs
– Logic Input Standards Compliance Set By VDDINP Pin
 CMOS 5.0, LVCMOS 3.3, LVCMOS 2.5
• 4 Open Drain Outputs
– Supports Various Interface Standards Through External Pull-Ups
• 8 Comparator Direct Outputs
– Logic Expansion
– Drive Voltage Tracking Transistors
– Easy interface to Existing System Level Initialization Logic
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Summary
Complete & Flexible Power Sequencing &
Monitoring Solution
• Integration
- Combines Analog & Digital Functionality
- Ruggedized Operation Increases Reliability
• Programmability
-
Threshold Voltages
CPLD for Sequencing, Monitoring Logic Implementation
FET Driver for Controlling Power Supply Ramp Rate
Programmable Long-Duration Timers
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Application Example
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Example Power Supply Problem Statement
Power Sequencing Application
Step - 1
Card Power
Turned On
Step - 2
Turn-on 1.8V
Supply for CPU
Step - 3
Turn-on 2.5V
Supply for ASIC
& CPU I/O
Step - 4
Turn-on 3.3V
Supply for ASIC
I/O & Other
Devices
Step - 5
Card Power-up
Complete
© LATTICE SEMICONDUCTOR CORPORATION 2002
•
Step-by-Step
Powering Up a
Multi-Voltage
Circuit Board
Supervisory Signal
Generation
1. Activate Power_OK signal
and Deactivate
CPU-Reset Signal After all
Supplies are Turned On
•
Monitoring Power Supply
Voltages
1. If Any Voltage Drops
Below Threshold, Reset
Processor & Remove All
Power
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Example Application
Device 3.3V Power Bus
2.5V
Brick
ASIC & I/O Voltage Bus
Other Board
Circuitry
Dev_2V5_Over2V4
Dev_1V8_Over1V7
Brick2V5_En
FET_Driver_3V3
Vin_3V3_Over3V2
CPU Core Voltage
LDO1V8_En
1.8V
LDO
3.3V
Input
Supply
CPU_Reset
Power_Good
PowerPAC1208
Power Supply Monitoring, Sequencing, &
Supervisory Signal Generation
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Power Supply Sequence Steps
STEP
CONDITION/ACTION
COMMENTS
1
Wait for 3.3 V supply > 3V
Wait for 3.3V to stabilize within 10% margin
2
Enable 1.8 LDO = 1, CPU-Reset = 0
Hold the reset active when the CPU is powered on
3
Wait for 1.8V > 1.7V
Wait for LDO voltage to stabilize
4
Enable 2.5V Power Supply Brick = 1
5
Wait for 2.5V supply > 2.375V
Wait for the 2.5V to stabilize within the 5% margin
6
Power-Good signal = 1
Signal to FPGA to Load
7
Wait for 50 ms
Wait for FPGA to load, and the ASIC to initialize
8
CPU-Reset = 1
CPU is now ready to execute
9
<Board Power up complete>
10
POWER-DOWN SEQUENCE
Enter here under fault condition
11
CPU-Reset = 0
Prevent CPU from corrupting memory
12
Enable 2.5V Power Supply Brick = 0;
Enable 1.8 LDO = 0
Remove the 2.5V power supply and remove the
1.8V supply to CPU
13
Jump to step 13
Stop
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Handling Power Supply Fault Condition
Monitor Condition
Outputs
Go to
Comments
Sequence
Step
IF (Power_good = 1) Power_good Step 10
AND
signal = 0
(( 3.3V is < 3V)
OR (2.5V < 2.375)
OR (1.8V < 1.71))
© LATTICE SEMICONDUCTOR CORPORATION 2002
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If one of the power
supply voltages drops
below lower limit,
initiate shut down
PAC-Designer 1.9.1
Demonstration
© LATTICE SEMICONDUCTOR CORPORATION 2002
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What’s New in PAC-Designer 1.9.1 - For PowerPAC
• Hierarchical Design Entry
– Easy System Interface Parametric Specification
• PAC LogiBuilder - The Logic Wizard
– Map Power Supply Sequencing & Monitoring Steps Directly into Design
 Advanced Features: Supply Glitch Monitor, Watchdog Timer, etc.
– Fits Code Into PLD Automatically
• Lattice Simulator
– Waveform Viewer
– Waveform Stimulus Editor
© LATTICE SEMICONDUCTOR CORPORATION 2002
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First .. High Level Design Entry
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Configure Supply Voltage Monitoring Threshold
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Summary – Hierarchical Design Entry
• Easy System Interface Parametric Specification
– Setting Monitor Threshold Voltage, Signal Names
– FET Gate Drive Voltage & Current
– Selecting Internal/External Clock & Timer Values
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Second: Build Sequence Control Program
No New Language to Learn!
Double-Click On
the Line &
Pick Instructions
From Menu
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And .. Build Expressions Interactively
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Detailed Application Requirement
Easily Translates Into PAC LogiBuilder Program
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And.. Fits into a PowerPAC1208!
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PAC LogiBuilder - Summary
• Intuitive Translation of Power Sequencing & Monitoring Requirement
– No New Language to Learn
– Simple Point & Click Instructions




Power Supply Sequence Design
Power Supply Monitor Design
Supervisory Signal Specification
5 Basic Instructions & 3 Advanced Instructions
– Fitting the Design into On-board CPLD of PowerPAC
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Third: Create Stimulus Using Waveform Editor
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Verify the Design Using The Lattice Simulator
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Finally: “ispProgram” the Device
PowerPAC Evaluation Board
JTAG
ispDOWNLOAD Cable
• Same Cable Used For Programming Lattice CPLD
© LATTICE SEMICONDUCTOR CORPORATION 2002
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PAC-Designer 1.9.1 - Summary
• Hierarchical System Interface Definition
– Easy System Interface Parametric Specification
• PAC LogiBuilder
– Easy Design of Sequencing & Monitoring
– Intuitive Point & Click Instructions
• Lattice Waveform Editing & Simulation
– Verify Design Before Wiring up Prototype
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Additional Documentation…..
• Application Notes
• Sparkle Sheet
• DataSheet
• PAC-Designer 1.9.1
© LATTICE SEMICONDUCTOR CORPORATION 2002
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PowerPAC1208 & PACsystem
• ispPAC-POWR1208-01T44I
– Available in 44-Pin TQFP Package Only
– Temperature Range - -40C to +85C
• Evaluation – PAC-SystemPOWR1208
– Evaluation Board – PAC-POWR1208-EV
– PAC-Designer 1.9.1 Software CD
• Includes Latest Datasheets & Applications Notes
– Price: $149
© LATTICE SEMICONDUCTOR CORPORATION 2002
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Summary
• Integration
– PowerPAC Offers Single-Chip Solution For Sequencing & Monitoring
– Board Space Savings
– Increased Reliability
• Software
– Simplifies Interfacing PowerPAC to Various Power Supplies & FETs
– PAC LogiBuilder – Easy Implementation of Sequencing and Monitoring
Algorithms
– Wave Stimulus and Waveform View Ease Verification
• Programmability
– Flexibility in Sequencing, Threshold Voltage, Delays, FET Gate Driver
– Inventory Reduction – PowerPAC can be Tailored to Control Many
Types of Power Supply Arrangements
– EECMOS Technology + ISP Allows Easy Tuning of Design
© LATTICE SEMICONDUCTOR CORPORATION 2002
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