Download Lecture 1 - Circuits & Layout

Lecture 1:
Circuits &
Layout
Outline

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
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A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
2
The First Computer
The Babbage
Difference Engine
(1832)
25.000 parts
cost: £17.470
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
3
ENIAC – The First Electronic Computer
(1946)
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
4
The Transistor Revolution
 Fi
First Transistor
Bell Labs
1948
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
5
A Brief History
 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
 2010
– Intel Core i7 mprocessor
• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE.
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
6
First Integrated Circuits
Bipolar Logic
1960’s
ECL 3-input
NAND Gate
Motorola
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
7
Intel 4004 Microprocessor
1971
1000 transistors
1 MHz operation
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
8
Growth Rate
 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
[Moore65]
Electronics Magazine
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
9
Annual Sales
 >1019 transistors manufactured in 2008
– 1 billion for every human on the planet
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives.
Reprinted with
permission.
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
11
Transistor Types
 Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
[Vadasz69]
© 1969 IEEE.
Intel
Museum.
Reprinted
with
permission.
Intel 1101 256-bit SRAM
Intel 4004 4-bit mProc
 1980s-present: CMOS processes for low idle power
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Moore’s Law
 In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months.
 He made a prediction that semiconductor
technology will double its effectiveness every 18
months
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Moore’s Law: Then
 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Integration Levels
SSI:
10 gates
MSI: 1000 gates
LSI:
[Moore65]
10,000 gates
VLSI: > 10k gates
Electronics Magazine
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
15
And Now…
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
16
Evolution in Complexity
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
17
Feature Size
 Minimum feature size shrinking 30% every 2-3 years
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Die Size Growth
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Corollaries
 Many other factors grow exponentially
– Ex: clock frequency, processor performance
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CMOS VLSI Design 4th Ed.
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Power Dissipation
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Power density
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
Year
2010
Power density too high to keep junctions at low temp
CMOS VLSI Design 4th Ed.
22
Courtesy, Intel
(M)
Productivity Trends
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip
1,000
1,000,000
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10,00010
100
100,000
1,0001
10
10,000
x
0.1
100
x x
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
CMOS VLSI Design 4th Ed.
23
Courtesy, ITRS Roadmap
Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …
– How to design chips with more and more functions?
– Design engineering population does not double every
two years…
 Hence, a need for more efficient design
methods
24
– Exploit different levels of abstraction
CMOS VLSI Design 4th Ed.
Design Metrics
 How to evaluate performance of a digital circuit
(gate, block, …)?
– Cost
– Reliability
– Scalability
– Speed (delay, operating frequency)
– Power dissipation
– Energy to perform a function
25
CMOS VLSI Design 4th Ed.
Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs
– design time and effort, mask generation
– one-time cost factor
 Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
26
CMOS VLSI Design 4th Ed.
NRE Cost is Increasing
27
CMOS VLSI Design 4th Ed.
Die Cost
Single die
Wafer
Going up to 12” (30cm)
28
From http://www.amd.com
CMOS VLSI Design 4th Ed.
Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
29
1985
1988
1991
1994
1997
2000
CMOS VLSI Design 4th Ed.
2003
2006
2009
2012
Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer 

die area
2  die area
30
CMOS VLSI Design 4th Ed.
Defects
 defects per unit area  die area 
die yield  1 




 is approximately 3
die cost  f (die area) 4
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CMOS VLSI Design 4th Ed.

Some Examples (1994)
Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/
cm2 mm2 wafer
Yield
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
32
CMOS VLSI Design 4th Ed.
CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
inputs
– a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
1: Circuits & Layout
0
CMOS VLSI Design 4th Ed.
pMOS
pull-up
network
output
nMOS
pull-down
network
34
Series and Parallel
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nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
a
a
0
g1
g2
(a)
a
g1
g2
(c)
a
g1
g2
b
(d)
CMOS VLSI Design 4th Ed.
0
1
b
b
OFF
OFF
OFF
ON
a
a
a
a
0
1
1
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
1
b
0
(b)
1
1
0
g2
a
b
a
g1
a
0
0
b
b
1: Circuits & Layout
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
35
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
Y
– Requires parallel pMOS
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Compound Gates
 Compound gates can do any inverting function
 Ex: Y  A B  C D (AND-AND-OR-INVERT, AOI22)
A
C
A
C
B
D
B
D
(a)
A
(b)
B C
D
(c)
C
D
A
B
(d)
C
D
A
B
A
B
C
D
Y
A
C
B
D
Y
(f)
(e)
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CMOS VLSI Design 4th Ed.
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Example: O3AI
 Y  A B C D
A
B
C
D
Y
D
A
1: Circuits & Layout
B
C
CMOS VLSI Design 4th Ed.
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Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Pass Transistors
 Transistors can be used as switches
g=0
g
s
s
d
d
g=1
s
g=1
d
s
s
d
s
d
CMOS VLSI Design 4th Ed.
degraded 1
g=0
0
g=1
d
1: Circuits & Layout
1
Input
g=0
g
Input g = 1 Output
0
strong 0
degraded 0
g=0
1
Output
strong 1
40
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
b
gb
1: Circuits & Layout
a
g
b
gb
Output
a
b
gb
CMOS VLSI Design 4th Ed.
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Tristates
 Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
EN
Y
A
EN
Y
A
EN
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
42
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
EN
A
Y
EN
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
43
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
44
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
1: Circuits & Layout
D0
0
Y
D1
CMOS VLSI Design 4th Ed.
1
45
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20
D1
S
D0
D1
S
D0
1: Circuits & Layout
Y
4
2
4
2
4
2
Y
2
CMOS VLSI Design 4th Ed.
46
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
– Only 4 transistors
S
D0
Y
S
D1
S
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
47
Inverting Mux
 Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter
D0
S
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
Y
S
D1
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
0
1
48
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
– Or four tristates
D0
S0
D0
S1
0
D1
D1
1
0
Y
Y
D2
0
D3
1
1
D2
D3
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
49
D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch
D
Latch
CLK
1: Circuits & Layout
CLK
D
Q
Q
CMOS VLSI Design 4th Ed.
50
D Latch Design
 Multiplexer chooses D or old Q
CLK
D
1
CLK
Q
Q
Q
D
Q
0
CLK
CLK
CLK
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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D Latch Operation
Q
D
CLK = 1
Q
Q
D
Q
CLK = 0
CLK
D
Q
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
52
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
D
Flop
D
Q
Q
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
53
D Flip-flop Design
 Built from master and slave D latches
CLK
CLK
CLK
QM
D
CLK
QM
Latch
D
Latch
CLK
CLK
CLK
CLK
Q
CLK
1: Circuits & Layout
Q
CMOS VLSI Design 4th Ed.
CLK
54
D Flip-flop Operation
D
QM
Q
CLK = 0
D
QM
Q
CLK = 1
CLK
D
Q
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
55
Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
D
Flop
CLK1
CLK2
Q2
Q1
Q2
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
56
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
2
1
QM
D
2
2
2
Q
1
1
1
1
2
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
57
Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
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Example: Inverter
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
59
Example: NAND3





Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
60
Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD
VDD
A
A
B
C
c
Y
GND
INV
1: Circuits & Layout
Y
GND
metal1
poly
ndiff
pdiff
contact
NAND3
CMOS VLSI Design 4th Ed.
61
Wiring Tracks
 A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
 Transistors also consume one wiring track
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
62
Well spacing
 Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
63
Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in l
40 l
32 l
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
64
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
–
Y  A B C D
VDD
A
B
C
D
Y
6 tracks =
48 l
GND
5 tracks =
40 l
1: Circuits & Layout
CMOS VLSI Design 4th Ed.
65