Download Access IC Lab

Chapter 2
Manufacturing
Process
and
CMOS Circuit
Layout
1st rev. : March 7, 2003
2nd rev. : April 10, 2003
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Manufacturing
CMOS Process
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Manufacturing
A Modern CMOS Process
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
poly
p-well
n+
SiO2
n-well
p+
p-epi
p+
Dual-Well Trench-Isolated CMOS Process
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Manufacturing
The Manufacturing Process
For a great tour through the IC manufacturing process
and its different steps, check
www.fullman.com/semiconductors/semiconductors.html
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Manufacturing
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
SiO
2
Si-substrate
(f) Final result after removal of resist
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Manufacturing
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
spin, rinse, dry
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Manufacturing
Recurring Process Steps

Diffusion and Ion Implantation: change dopant
concentration of some parts of the material.

Deposition: Silicon Nitride Si3N4 (CVD, chemical
vapor deposition, Polysilicon (polycrystalline
silicon), Aluminum

Etching: Si2O (acid), Plasma etching (dry etching)

Planarization: Chemical-mechanical planarization
(CMP) on top of Si2O before deposition of an extra
metal layer.
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Manufacturing
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
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Manufacturing
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
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p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
p+
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
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Manufacturing
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
(e) After n-well and
V
adjust implants
Tp
(f) After p-well and
V
adjust implants
Tn
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Manufacturing
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
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Manufacturing
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
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Manufacturing
Advanced Metallization
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Manufacturing
Advanced Metallization
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Manufacturing
Design Rules
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Manufacturing
3D Perspective
Polysilicon
Aluminum
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Manufacturing
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
Vout2
M3
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Manufacturing
Its Layout View
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Manufacturing
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
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Manufacturing
Layers in 0.25 mm CMOS process
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Manufacturing
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
+
n
+
p
Field
Oxide
(b) Cross-Section along A-A’
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Manufacturing
Sticks Diagram
V DD
3
Out
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
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Manufacturing
Design Rules
Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)

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Manufacturing
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
2
3
4
Metal2
3
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Manufacturing
Transistor
Transistor Rules (DRC)
1
3
2
5
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Manufacturing
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
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Manufacturing
Select Layer
2
3
Select
2
1
3
3
2
Substrate
5
Well
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Manufacturing
Layout Editor (Cadence, Magic,..)
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Manufacturing
Design Rule Checker (on-line check)
poly_not_fet to all_diff minimum spacing = 0.14 um.
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Manufacturing
CMOS Layout of
Complexe Gate:
From Chapter 6
Slides and Insert D
Designing Combinational
Logic Circuits
March 28, 2003
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Manufacturing
Example Gate: NAND
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Manufacturing
Example Gate: NOR
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Manufacturing
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
C
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Manufacturing
Constructing a Complex Gate
OUT = D + A • (B + C)
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
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Manufacturing
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
GND
A B
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Manufacturing
Stick Diagrams
Logic Graph
A
j
X
C
C
B
X = C • (A + B)
C
A
i
i
X
B
B
PUN
A
B
C
VDD
j
GND
A
PDN
PUN: Pull-up Network, PDN: Pull-down Network
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Manufacturing
Two Versions of C • (A + B)
A
C
B
A
B
C
VDD
VDD
X
GND
Two Strips Line of Diffusions
X
GND
One Strip Line of Diffusions
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Manufacturing
Consistent Euler Path
(Insert D of textbook)
X
C
i
X
B
VDD
j
GND
A
A B C
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Manufacturing
OAI22 Logic Graph
A
C
B
D
X
D
X = (A+B)•(C+D)
C
D
A
B
C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
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Manufacturing
Example: x = ab+cd
x
x
c
b
VDD
x
a
c
b
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
Euler Paths
For both PUD
and PDN
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
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Manufacturing
Cell Design
 Standard
Cells (gate collection)
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath
Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width
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Manufacturing
Standard Cell Layout Methodology –
1980s
VDD
Routing
channel
VDD
signals
GND
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Manufacturing
Standard Cell Layout Methodology –
1990s
Mirrored Cell
No Routing
channels
VDD
VDD
M2
M3
GND
GND
Mirrored Cell
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Manufacturing
Standard Cells
N Well
VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
2
Cell boundary
In
Out
GND
Rails ~10
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Manufacturing
Standard Cells
With minimal
diffusion
routing
VDD
With silicided
diffusion
VDD
VDD
M2
In
Out
In
Out
In
Out
M1
GND
GND
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Manufacturing
Standard Cells
VDD
2-input NAND gate
VDD
B
A
B
Out
A
GND
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Manufacturing
CMOS Fabrication and Layout
•See the supplement data in Web!
•http://access.ee.ntu.edu.tw
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Manufacturing