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Optoelectronic Multi-Chip Modules Donald M. Chiarulli, Steven P. Levitan, Jason D. Bakos University of Pittsburgh, Pittsburgh PA USA Optoelectronic Chips VCSEL ARRAY SoS CMOS logic chip Demonstrator System Two image guide segments, right segment cut on bias to fiber direction OE component bonded to FIG Chip layout Chip with 8x8 receiver shown from top Demonstrator system Underside of chip die showing receivers VCSEL site 64x64 VCSEL array shown through bottom of chip Receiver site Closeup of VCSELs shown through bottom of chip Alignment mark for chip alignment (through optic) Closeup of receiver shown through die Wireframe view of MCM interconnect Fiber Image Guide Optic with mounted chip Assembled OE chip bonded to PCB Optic shown with backlight Chip top shown through PCB cavity Chip bottom Side of optic showing fiber direction
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