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ISSUES IN TIMING
Digital Integrated Circuits
Timing
© Prentice Hall 1995
The Clock Skew Problem
Clock Rates as High as 500 Mhz in CMOS!

t’
In
CL1
R1
ti
t’’
CL2
R2
t ’’’
CL3
R3
Out
tl,min t r,min
tl,max t r,max
Clock Edge Timing Depends upon Position
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Delay of Clock Wire
RS
r
c
CL
r = 0.07  /q, c = 0.04 fF/ m2
(Tungsten wire)
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Constraints on Skew
’
t’

tr,min + tl,min + ti
R1
’’
t’’ = t’ + 
R2
data
(a) Race between clock and data.
’
t’

’’
t’’ + T =
t’ + T
tr,max + tl,max + ti
R1
’’+ T
R2
data
(b) Data should be stable before clock pulse is applied.
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Constraints in Edge-Triggered Logic
  t r min + t i + t l min
T  t r max + t i + t l max – 
Maximum Clock Skew Determined by Minimum Delay between Latches
Minimum Clock Period Determined by Maximum Delay between Latches
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Positive and Negative Skew

Data
(a) Positive skew
CL
R
CL
R
CL
R

Data
(b) Negative skew
CL
Digital Integrated Circuits
R
CL
R
Timing
CL
R
© Prentice Hall 1995
Clock Skew in Master-Slave Two Phase Design
CL1
CL2
CL3
M3
S3
In
 ’
M2
S2
 ’
M1
S1



Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Skew in 2-phase design
new data applied to CL2
previous data latched into M2
1
T
T
2
1’
T

T
clock
overlap
 T
clock period T
tmin >  - T12
tmax  T T
Digital Integrated Circuits
Timing
© Prentice Hall 1995
How to counter Clock Skew?


.
REG
REG
In

REG
REG
Negative Skew
log
Out

Positive Skew
Clock Distribution
Data and Clock Routing
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Distribution
CLOCK
H-Tree Network
Observe: Only Relative Skew is Important
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Network with Distributed
Buffering
Local Area
Module
Module
secondary clock drivers
Module
Module
Module
Module
main clock driver
CLOCK
Reduces absolute delay, and makes Power-Down easier
Sensitive to variations in Buffer Delay
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
• Single 6-stage driver at center of chip
• Secondary buffers drive left and right side
clock grid in Metal3 and Metal4
Total driver size: 58 cm!
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Drivers
Digital Integrated Circuits
Timing
© Prentice Hall 1995
Clock Skew in Alpha Processor
Digital Integrated Circuits
Timing
© Prentice Hall 1995