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PLD
(Programmable Logic Device)
ARINDAM CHAKRABORTY
LECTURER,DEPT. OF ECE
INSTITUTE OF ENGINEERING & MANAGEMENT
Tuesday, May 23, 2017
1
ICs
EVOLUTION
COMPLEXITY
1905 : Mount Road -Madras
2005: Mount Road -Madras
Integrated Circuit Revolution
1958:First integrated circuit (germanium)
Built by Jack Kilbyat Texas Instruments
components :Transistors, Resistors and
Capacitors
2000: Intel Pentium 4 Processor
Clock speed: 1.5 GHz
Transistors: 42 million
Technology: 0.18μm CMOS
If Transistors are Counted as Seconds
Chip
4004
8080
8086
Time
< 1 hr
< 2 hrs
8 hrs
80286
80386 DX
80486
1.5 days
3 days
13 days
Pentium
Pentium Pro
P II
P III
> 1 month
2 months
3 months
~1 year
P4
~ 1.5 years
Evolution of VLSI
•SSI–Small Scale Integration (GATE < 10 )
•MSI–Medium Scale Integration (10 < GATE < 1000)
Demanded automation of design process Computer Aid Design started evolving
•LSI–Large Scale Integration (GATE > 1000)
•VLSI–Very Large Scale Integration ( GATE > 100000)
Before Tools
•Laid out 4004 by hand
–Drawn on paper and photographed
–Demagnified 500 times smaller
•Almost no verification or validation
–Chips may not function properly
–Market may return products
SOLUTION !
Evolution of CAD Tools
VLSI chip design forced
•Automation of process
•Automation of Simulation based verification
REPLACING
Breadboard Techniques
HDL Development
Comparison of Sizes
How Small Are The Transistors?
Processor Power Trends
Evolution in IC Complexity
Design Goals Over Time
COMPLEXITY
1905 : Mount Road -Madras
2005: Mount Road -Madras
Read Only Memory (ROM)
‘m’
‘n’
A
B
F1
 IT IS TRUTH TABLE IN A HARDWARE FORM
OR
WE CAN SAY HARDWARE FOR TRUTH TABLE
ROM
F2
Ci
 SIZE OF ROM:FOR, ‘n’ No. OF INPUT AND ‘m’ No. OF OUTPUT
SIZE =2 n x m BITS
ROM
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Read Only Memory (ROM)
ai
bi
DECODER
(AND ARRAY)
Ci-1
m0
m1
m2
m3
m4
m5
m6
m7
Si
Ci
APPLYING 1-BIT FULL ADDER
Si = F (1,2,4,7)
Ci = F (3,5,6,7)
Tuesday, May 23, 2017
DECODER DESIGN
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Read only memory (ROM)
ROM holds programs and data permanently even when computer is switched off
Data can be read by the CPU in any order so ROM is also direct access
The contents of ROM are fixed at the time of manufacture
Access time of between 10 and 50 nanoseconds
PLD
(PROGRAMMABLE LOGIC DEVICE)
PLD
•PROGRAMMABLE ::
I CAN CHANGE THE APPLICATION
•LOGIC ::
THE VALIDITY OF AN ARGUMENT IS DETERMINED
BY ITS LOGICAL FORM
•DEVICE ::
MACHINE
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• Programmable Logic Device(PLD):
A programmable logic devices is an IC’s that user configurable
and is capable of implementing logic function
• PLDs ARE :I . COMBINATIONAL PLDs
II . SEQUENTIAL PLDs
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I . C O M B I N AT I O N A L
PROGRAMMABLE LOGIC DEVICE (PLD):
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DIFFERENT TYPES OF COMBINATIONAL PLDs :A. Programmable Read Only Memory (PROM) :
Output
Input
Fixed AND Array
(Decoder)
B . P r o g r a m m a b l e A r r a y L o g i c ( PA L ) :
Programmable OR
Array
Output
Input
Programmable AND
Array
C. Programmable Logic Array (PLA) :
Fixed OR
Array
Output
Input
Programmable AND
Array
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Programmable OR
Array
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DIFFERENT TYPEs OF ROM:ROM (AND & OR ARRAY BOTH ARE FIXED)
PROM (FIXED AND ARRAY & PROGRAMMABLE OR ARRAY)
EPROM (ERASABLE PROM> TO CHANGE MORE TIME)
UVEPROM (OLD TECH.> TO CHANGE THE LOGIC USING UV RAY)
EEPROM(ELECTRICALLY ERASABLE PROM> APPLYING ELEC. PULSES)
EAPROM(ELECTRICALLY ALTERABLE PROM> NEW TECH) OR FLASH MEMORY
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Types of ROM
1. Programmable Read Only Memory (PROM)
• Empty of data when manufactured
• May be permanently programmed by the user
2. Erasable Programmable Read Only Memory (EPROM)
• Can be programmed, erased and reprogrammed
• The EPROM chip has a small window on top allowing it to be erased by shining
ultra-violet light on it
• After reprogramming the window is covered to prevent new contents being erased
• Access time is around 45 – 90 nanoseconds
Note: a nanosecond is one billionth of a second!
Types of ROM
3. Electrically Erasable Programmable Read Only Memory (EEPROM)
• Reprogrammed electrically without using ultraviolet light
• Must be removed from the computer and placed in a special machine to do this
• Access times between 45 and 200 nanoseconds
4. Flash ROM
• Similar to EEPROM
• However, can be reprogrammed while still in the computer
• Easier to upgrade programs stored in Flash ROM
• Used to store programs in devices
• Access time is around 45 – 90 nanoseconds
Note: a nanosecond is one billionth of a second!
DIFFERENT TYPEs OF ROM:-
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DIFFERENT TYPES OF COMBINATIONAL PLDs :-
A. Programmable Read Only Memory (PROM) :
Output
Input
Fixed AND Array
(Decoder)
Programmable OR
Array
(A) Programmable Read Only Memory (PROM)
ai
bi
AND
ARRAY
Ci-1
m0
m1
m2
m3
m4
m5
OR ARRAY
m6
m7
APPLYING 1-BIT FULL ADDER
Si = F (1,2,4,7)
Ci = F (3,5,6,7)
Si
Ci
FIXED AND ARRAY & PROGRAMMABLE OR ARRAY
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DIFFERENT TYPES OF COMBINATIONAL PLDs :-
B . P r o g r a m m a b l e A r r a y L o g i c ( PA L ) :
Output
Input
Programmable AND
Array
Fixed OR
Array
Tuesday, May 23, 2017
( B) PROGRAMMABLE ARRARY LOGIC ( PAL ) :-
X
Y
Z
P0
P1
PA L
P1
P2
P3
P4
P5
P0
F1= XY + X’Z
P3
P2
F1
F2= Y’ + X’Z
P5
F3= XY + Y’Z
F2
F3
P4
PROGRAMMABLE AND ARRAY & FIXED OR ARRAY
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PAL Table (Specifications):
P0
P1
P2
P3
P4
P5
F1
YES
YES
NIL
NIL
NIL
NIL
F2
NIL
NIL
YES
YES
NIL
NIL
F3
NIL
NIL
NIL
NIL
YES
YES
SIZE OF PAL :
 3 INPUTs
 3 OUTPUT
 6 PRODUCT TERM
 2 FOR EACH OUTPUT
DIFFERENT TYPES OF COMBINATIONAL PLDs :-
C. Programmable Logic Array (PLA) :
Output
Input
Programmable AND
Array
Programmable OR
Array
( C ) PROGRAMMABLE LOGIC ARRARY ( PLA ) :OR ARRAY
P0
A
P1
B
AND
ARRAY
C
P2
P3
PRODUCT TERM
F1
F2
PROGRAMMABLE AND ARRAY & PROGRAMMABLE OR ARRAY
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Tuesday, May 23, 2017
( C) PROGRAMMABLE LOGIC ARRARY ( PLA ) :-
X
Y
Z
P0
P1
PLA
P2
P3
F1= XY +
P1
X ’ Z P0
F2=
X ’ Z P0
Y’
P2
+
F 3 =P X Y +
1
F1
F2
F3
Y ’ Z P3
PROGRAMMABLE AND ARRAY & PROGRAMMABLE OR ARRAY
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PLA Table (Specifications):
P0
P1
P2
P3
F1
YES
YES
NIL
NIL
F2
YES
NIL
YES
NIL
F3
NIL
YES
NIL
YES
SIZE OF PLA :
 3 INPUTs
 4 PRODUCT TERM
 3 OUTPUT
Design PAL :
PAL Table (Specifications):
P0
P1
P2
P3
P4
P5
F1
YES
YES
NIL
NIL
NIL
NIL
F2
NIL
NIL
YES
YES
NIL
NIL
F3
NIL
NIL
NIL
NIL
YES
YES
SIZE OF PAL :
 3 INPUTs
 6 PRODUCT TERM
 3 OUTPUT
 2 FOR EACH OUTPUT
F1(a,b,c) = ∑m (0,2)
F2(a,b,c) = ∑m (0,3,4)
F3(a,b,c) = ∑m (0,3,4,7)
Design PLA :
PLA Table (Specifications):
P0
P1
P2
P3
P4
P5
F1
YES
NIL
NIL
NIL
NIL
NIL
F2
NIL
YES
YES
NIL
NIL
NIL
F3
NIL
NIL
NIL
YES
YES
NIL
SIZE OF PLA :
 3 INPUTs
 6 PRODUCT TERM
 3 OUTPUT
F1(a,b,c) = ∑m (0,2)
F2(a,b,c) = ∑m (0,3,4)
F3(a,b,c) = ∑m (0,3,4,7)
Programmable Array Logic (PAL) & Programmable Logic Array (PLA) :
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II . SEQUENTIAL
PROGRAMMABLE LOGIC DEVICE (PLD):
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DIFFERENT TYPES OF SEQUENTIAL PLDs :A. SIMPLE PROGRAMMABLE LOGIC DEVICE (SPLD) :
B. COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD):
C. FIELD PROGRAMMABLE GATE ARRAY (FPGA) :
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(I) SIMPLE PROGRAMMABLE LOGIC DEVICE (SPLD) ::
INPUT
OUTPUT
•A n S P L D c a n i m p l e m e n t h u n d r e d s o f g a t e s
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WHY CPLD?
• In case of the 7400 IC, 4 circuits of 2 input NAND gate
are
housed. In case of 7404, 6 circuits of inverter are housed.
• In case of CPLD, it has wiring among the logic in the IC. So,
the wiring on the printed board can be made little.
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(II) COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD)::
PROGRAMMABLE SWITCH
M AT R I X
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• Example CPLD Families ::
 Altera MAX 7000 and MAX 9000 families
 A t m e l AT F a n d AT V f a m i l i e s
 Lattice ispLSI family
 L a t t i c e ( Va n t i s ) M A C H f a m i l y
 Xilinx XC9500 family
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CPLD EXAMPLE ::
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(III) FIELD PROGRAMMABLE GATE ARRAY ::
• FPGA,
first
introduced
by
Xilinx
in
1984.
• It is a reprogrammable logic device that
implements multilevel logic.
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Tuesday, May 23, 2017
FPGA ::
CLB
CLB
CLB
IO
CLB
CLB
CLB
CLB
CLB
IO
CLB
CLB
CLB
CLB
CLB
IO
IO
CLB
CLB
CLB
CLB
CLB
IO
IO
IO
IO
IO
CLB
CLB
 Configurable Logic Block (CLB)
 Programmable Interconnect
 IO Block
IO
IO
IO
IO
IO
IO
IO
IO
IO
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Elements of an FPGA
• Logic Element (LE).
• Interconnect.
• I/O pins.
IOB
LE
IOB
IOB
LE
…
LE
interconnect
LE
LE
…
LE
LE
LE
LE
Configurable Logic Blocks:-
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Programmable Interconnect::
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Configurable I/O Blocks::
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Example FPGA Families::
S R A M b a s e d F P G A f a m i l i e s
A l t e r a F L E X f a m i l y
A t m e l AT 6 0 0 0 a n d AT 4 0 K f a m i l i e s
L u c e n t Te c h n o l o g i e s O R C A f a m i l y
X i l i n x XC 4 0 0 0 a n d V i r t e x f a m i l i e s
A n t i - f u s e b a s e d F P G A f a m i l i e s
A c t e l S X a n d M X f a m i l i e s
Q u i c k l o g i c p A S I C f a m i l y
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• Choosing Between CPLDs and FPGAs ::
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CPLD Vs. FPGA : :
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T H A N K YO U
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