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CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure José Nelson Amaral CMPUT 229 - Computer Organization and Architecture I 1 Reading Material Patt & Patel, Chapter 3 CMPUT 229 - Computer Organization and Architecture I 2 The Light Switch CMPUT 229 - Computer Organization and Architecture I 3 A N-MOS transistor Gate 2.9 Volt battery (power supply) Gate Gate A Metal-Oxide Semiconductor (MOS) transistor has three terminals. The Gate controls the flow of electrons between the two other terminals. In a N-type MOS transistor, electrons will flow when a voltage of 2.9 V is applied to the Gate (closed circuit). If 0.0 V is applied to the Gate no electrons will flow (open circuit). CMPUT 229 - Computer Organization and Architecture I 4 The NOT Gate Problem: Use two MOS transistors to implement the following logic circuit: 2.9 Volts In NOT Out 0 Volts Your NOT circuit should implement the following logic function: In Out 0 Volts 2.9 Volts 2.9 Volts 0 Volts CMPUT 229 - Computer Organization and Architecture I 5 P-MOS Transistor #1 Gate #2 The operation of a P-type MOS transistor, is the opposite of an N-MOS: - electrons will flow when a voltage of 0.0 V is applied to the Gate (closed circuit). - If 2.9 V is applied to the Gate no electrons will flow (open circuit). CMPUT 229 - Computer Organization and Architecture I 6 The NOT Gate 2.9 Volts In Out 0 Volts 2.9 Volts 0V 2.9V 2.9 Volts 2.9V 0 Volts In Out 0 Volts 2.9 Volts CMPUT 229 - Computer 2.9 Volts 0 Volts Organization and Architecture I 0V 0 Volts In Out 0 1 1 0 7 A B C 0 Volts 0 Volts 2.9 Volts The NOR Gate A A= 0V B B=0V C CMPUT 229 - Computer Organization and Architecture I C= 2.9V 8 A B C 0 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts The NOR Gate A A= 0V B B=2.9V C CMPUT 229 - Computer Organization and Architecture I C= 0V 9 A B C 0 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts 0 Volts The NOR Gate A A= 2.9V B B= 0V C CMPUT 229 - Computer Organization and Architecture I C= 0V 10 A B C 0 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts 2.9 Volts 0 Volts 0 Volts 2.9 Volts 2.9 Volts 0 Volts The NOR Gate A A= 2.9V B B= 2.9V C CMPUT 229 - Computer Organization and Architecture I A 0 0 1 1 B 0 1 0 1 C 1 0 0 0 C= 0V 11 What Logic Function this Circuit Implements? A 0 0 1 1 A B B 0 1 0 1 C 1 0 0 0 D 0 1 1 1 1 C D This is an OR gate. CMPUT 229 - Computer Organization and Architecture I 12 The AND Gate A 0 0 1 1 A B C D CMPUT 229 - Computer Organization and Architecture I B 0 1 0 1 C 1 1 1 0 D 0 0 0 1 1 13 Logic Functions INVERTER X X’ AND A B C=A·B OR A B C=A+B X’ 1 0 X 0 1 A 0 0 1 1 B 0 1 0 1 If X=0 then X’=1 If X=1 then X’=0 C 0 0 0 1 A B C 0 0 0 0 1 1 1 0 1 CMPUT 229 Computer 1 1 1 Organization and Architecture I If A=1 AND B=1 then C=1 otherwise C=0 If A=1 OR B=1 then C=1 otherwise C=0 14 NOR and NAND Because these combination of gates are used often, there are special symbols to represent them: X Y Z X Y Z X Y Z X Y Z CMPUT 229 - Computer Organization and Architecture I 15 First DeMorgan’s Law (X+Y)’ = X’Y’ X Y Z X Z Y The complement of the OR is equal the AND of the complements. X 0 0 1 1 Y 0 1 0 1 X+Y 0 1 1 1 (X+Y)’ 1 0 0 0 X’ 1 1 0 0 Y’ 1 0 1 0 CMPUT 229 - Computer Organization and Architecture I X’Y’ 1 0 0 0 16 Decoders General decoder structure Typically n inputs, 2n - outputs CMPUT 229 Computer Organization and Architecture I 2-to-4, 3-to-8, 4-to-16, etc. 17 Decoders a b c 3-to-8 Line Decoder y0 = a’b’c’ y1 = a’b’c y2 = a’bc’ y3 = a’bc y4 = ab’c’ y5 = ab’c y6 = abc’ y7 = abc + a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 CMPUT 229 - Computer Organization and Architecture I c 0 1 0 1 0 1 0 1 y0 1 0 0 0 0 0 0 0 y1 0 1 0 0 0 0 0 0 y2 0 0 1 0 0 0 0 0 y3 0 0 0 1 0 0 0 0 y4 0 0 0 0 1 0 0 0 y5 0 0 0 0 0 1 0 0 y6 0 0 0 0 0 0 1 0 y7 0 0 0 0 0 0 0 1 18 Multiplexers I0 I1 4-to-1 MUX I2 I3 A A 0 0 1 1 + B B 0 1 0 1 Z I0 I1 I2 I3 Z A’ B’ I0 A’ B I1 Z A B’ I2 A B I3 CMPUT 229 - Computer Organization and Architecture I 19 Adders Basic building block is “full adder” 1-bit-wide adder, produces sum and carry outputs X Y Cin S Cout 0 0 0 0 0 1 Cout is one if two or more of the inputs are one. 0 1 0 0 1 1 1 0 0 S is one if an odd number 1 0 1 of inputs are one. 1 1 0 1 1 1 CMPUT 229 - Computer Organization and Architecture I 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 20 Full-adder circuit CMPUT 229 - Computer Organization and Architecture I 21 Ripple adder Speed limited by carry chain Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2n product terms 3 or 4 levels of logic, carry lookahead CMPUT 229 - Computer Organization and Architecture I 22 A bi-stable circuit How to control it? Control inputs S-R latch CMPUT 229 - Computer Organization and Architecture I 23 D latch CMPUT 229 - Computer Organization and Architecture I 24 DIN3 0 3-to-8 decoder 1 2 0 A2 1 A1 1 A0 2 3 1 0 4 5 6 7 WE_L CS_L DIN2 DIN1 DIN0 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WR_L IOE_L OE_L DOUT3 DOUT2 DOUT1 DOUT0 DIN3 0 3-to-8 decoder 1 2 0 A2 1 A1 1 A0 2 3 1 0 4 5 6 7 WE_L CS_L DIN3 DIN3 DIN3 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WR_L IOE_L OE_L DOUT3 DOUT3 DOUT3 DOUT3 DIN3 0 3-to-8 decoder 1 2 0 A2 1 A1 1 A0 2 3 1 0 4 5 6 7 WE_L CS_L DIN3 DIN3 DIN3 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WR_L IOE_L OE_L DOUT3 DOUT3 DOUT3 DOUT3 DIN3 0 3-to-8 decoder 1 2 0 A2 1 A1 1 A0 2 3 1 0 4 5 6 7 WE_L CS_L DIN3 DIN3 DIN3 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WR_L IOE_L OE_L DOUT3 DOUT3 DOUT3 DOUT3