Download Chapter Fifteen

Introduction
to
Electronic Circuit Design
Richard R. Spencer
Mohammed S. Ghausi
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 1
Figure 15-1 (a) A diode switching circuit. (b) The waveforms for the circuit.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 2
Figure A15-1 (a) A diode switching circuit. (b) The waveforms for
the circuit. (c) The minority-carrier densities on the p side of the
junction as a function of time while the diode is turning on; the
dashed line is the edge of the depletion region. (d) The minoritycarrier densities on the p side of the junction as a function of time
while the diode is turning off; the dashed line is the edge of the
depletion region.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 3
Figure 15-7 (a) A BJT switching circuit. (b) The
waveforms for the circuit.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 4
Figure 15-8 (a) The minority-carrier profile in a BJT in forwardactive operation. (b) The profile in saturation, showing that it is the
superposition of the forward- and reverse-active profiles.
Figure 15-9 (a) The minority-carrier profile in a BJT in saturation.
(b) The profile as the transistor is taken out of saturation.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 5
Figure 15-12 (a) An inverter. (b) The DC transfer characteristic.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 6
Figure 15-13 (a) Two gates in series. (b) A one-dimensional plot of the
input and output voltage specifications.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 7
Figure 15-15 Illustration of propagation
delay and transition times.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 8
Figure 15-22 A CMOS inverter.
Figure 15-24 The DC transfer characteristic
of an ideal symmetric CMOS inverter.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 9
Figure 15-26 (a) A CMOS inverter with capacitive load. (b) The
input and output waveforms for calculating tPHL.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 10
Figure 15-28 (a) A CMOS inverter, (b) a simplified layout of the inverter, and (c) the
parasitic SCR.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 11
Figure 15-29 A NOR gate using NMOS
transistors and an unspecified pull-up circuit.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 12
Figure 15-30 A two-input CMOS NOR gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 13
Figure 15-32 A two-input CMOS NAND gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 14
Figure 15-34 A CMOS gate to implement (15.58).
(15.58)
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 15
Figure 15-36 (a) A CMOS
transmission gate and (b)
the schematic symbol for it.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 16
(b)
Figure A15-6 (a) A single NMOS switch
and (b) a CMOS transmission gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 17
Figure 15-37 A four-to-one multiplexer circuit.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 18
Figure 15-38 The architecture of a large
semiconductor memory.
Figure 15-39 The architecture of one of the
sub arrays in Figure 15-38.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 19
Figure 15-40 The six-transistor SRAM cell. (a) The circuit with the latch shown as
coupled inverters and (b) the transistor-level schematic.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 20
Figure 15-42 A one-transistor DRAM memory cell.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 21
Figure 15-43 The upper-left 16 bits of a NOR ROM array.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 22
Figure 15-48 A DRAM sense amplifier.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 23
Figure 15-51 A basic two-input TTL NAND gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 24
Figure 15-54 A 2-input TTL NOR gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 25
Figure 15-60 An ECL OR-NOR gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 26
Figure 15-73 The bias circuit for 10K family ECL circuits shown with the
rest of the gate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc.
Chapter 15, slide 27