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COMBINATIONAL
LOGIC
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Combinational vs. Sequential Logic
In
Logic
In
Circuit
Out
Logic
Out
Circuit
State
(a) Combinational
Output = f(In)
Digital Integrated Circuits
(b) Sequential
Output = f(In, Previous In)
Combinational Logic
© Prentice Hall 1995
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Static CMOS
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Complementary CMOS Logic Style Construction (cont.)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A• (B+C)
A
D
B
Digital Integrated Circuits
C
Combinational Logic
© Prentice Hall 1995
4-input NAND Gate
Vdd
VDD
VDD
In1
In2
In3
In4
Out
In1
In2
Out
In3
Out
In4
GND
In1 In2 In3 In4
GND
In1 In2 In3 In4
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Properties of Complementary CMOS Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
1
B
Digital Integrated Circuits
2
2 C
2
Combinational Logic
© Prentice Hall 1995
Propagation Delay Analysis - The Switch
Model
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
What is the Value of Ron?
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Numerical Examples of Resistances for 1.2mm
CMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
A
D
2
1
B
2C
2
Here it is assumed that Rp = Rn
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Influence of Fan-In and Fan-Out
on Delay
VDD
A
B
C
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
D
t
Digital Integrated Circuits
p
= a FI + a FI 2 + a FO
1
2
3
Combinational Logic
© Prentice Hall 1995
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design
Techniques
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Digital Integrated Circuits
Distributed RC-line
Can Reduce Delay with more than 30%!
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(2)
• Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
Digital Integrated Circuits
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(3)
• Improved Logic Design
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(4)
• Buffering: Isolate Fan-in from Fan-out
CL
CL
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
A
B
Co = AB + C i(A+B)
28 transistors
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
A Revised Adder Circuit
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
B
A
B
Ci
A
B
24 transistors
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
F
In1
In2
In3
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
• VOL =
RPN + RL
F
In1
In2
In3
• Assymetrical response
PDN
• Static power consumption
VSS
Digital Integrated Circuits
RPN
• tpL= 0.69 RLCL
Combinational Logic
© Prentice Hall 1995
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
F
In1
In2
In3
PDN
VSS
depletion load NMOS
Digital Integrated Circuits
VSS
pseudo-NMOS
Combinational Logic
© Prentice Hall 1995
Load Lines of Ratioed Gates
IL(Normalized)
1
Current source
0.75
0.5
Pseudo-NMOS
Depletion load
0.25
Resistive load
0
0.0
Digital Integrated Circuits
1.0
2.0
3.0
Vout (V)
Combinational Logic
4.0
5.0
© Prentice Hall 1995
Pseudo-NMOS
VDD
A
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
2
V OL
kp


2
k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
2 
2

kp
V OL =  VDD – V T  1 – 1 – -----(assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Pseudo-NMOS NAND Gate
VDD
GND
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
B
C
D
CL
Adaptive Load
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Improved Loads (2)
VDD
VDD
M1
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
Dual Cascode Voltage Switch Logic (DCVSL)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example
Out
Out
B
B
A
B
B
A
XOR-NXOR gate
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
NMOS-only switch
C=5V
C=5V
M2
A=5V
A=5V
B
B
Mn
M1
CL
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes
static power consumption
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Solution 1: Transmission Gate
C
A
C
A
B
B
C
C
C=5 V
A=5V
B
CL
C=0V
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
R (Ohm)
20000.0
Rp
10000.0
0.0
0.0
Req
1.0
2.0
3.0
4.0
5.0
Vout
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
Digital Integrated Circuits
Combinational Logic
In2
© Prentice Hall 1995
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Delay in Transmission Gate Networks
5
5
V1
In
5
Vi
Vi-1
C
0
5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
CC
C
(c)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Elmore Delay (Chapter 8)
Vin
R1
C1
1
R2
Ri-1
2
C2
i-1
Ci-1
Ri
i
Ci
RN
N
CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N
N =
Digital Integrated Circuits
N
N
i
 Ri  Cj =  C i  R j
i=1 j=i
i=1 j=1
Combinational Logic
© Prentice Hall 1995
Delay Optimization
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
S Sum Generation
Ci
P
B
VDD
A
P
Co Carry Generation
Ci
A
Setup
Digital Integrated Circuits
VDD
P
Combinational Logic
© Prentice Hall 1995
(2) NMOS Only Logic: Level Restoring
Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Level Restoring Transistor
5.0
with
5.0
3.0
VB
1.0
-1.00
without
3.0
with
VX
Vout (V)
without
2
t (nsec)
1.0
4
(a) Output node
Digital Integrated Circuits
6 -1.00
2
4
6
t (nsec)
(b) Intermediate node X
Combinational Logic
© Prentice Hall 1995