Download The AND Gate

Faculty of Computer Science
Digital Logic
From Switches to Memories
CMPUT 229
© 2006
Department of Computing Science
Reading Material
 These slides are based on the Text by Patt and
Patel: Introduction to Computing Systems: From
Bits & Gates to C & Beyond.
 The concepts covered here are presented in
Chapter 2 of Alan Clements’ textbook.
CMPUT 229
© 2006
Department of Computing Science
The Light Switch
CMPUT 229
© 2006
Department of Computing Science
A N-MOS transistor
Gate
2.9 Volt
battery
(power
supply)
Gate
Gate
A Metal-Oxide Semiconductor (MOS) transistor has three terminals.
The Gate controls the flow of electrons between the two other terminals.
In a N-type MOS transistor, electrons will flow when a voltage of 2.9 V
is applied to the Gate (closed circuit).
If 0.0 V is applied to the Gate no electrons will flow (open circuit).
CMPUT 229
© 2006
Department of Computing Science
P-MOS Transistor
#1
Gate
#2
The operation of a P-type MOS transistor, is the opposite of an N-MOS:
- electrons will flow when a voltage of 0.0 V is applied
to the Gate (closed circuit).
- If 2.9 V is applied to the Gate no electrons will flow (open circuit).
CMPUT 229
© 2006
Department of Computing Science
The NOT Gate
Problem: Use two MOS transistors to implement the following
logic circuit:
2.9 Volts
In
NOT
Out
0 Volts
Your NOT circuit should implement the following logic function:
In
Out
0 Volts 2.9 Volts
2.9 Volts 0 Volts
CMPUT 229
© 2006
Department of Computing Science
The NOT Gate
2.9 Volts
In
Out
2.9 Volts
0V
2.9V
0 Volts
2.9 Volts
2.9V
0V
0 Volts
In
Out
0 Volts 2.9 Volts
2.9 Volts 0 Volts
CMPUT 229
0 Volts
In Out
0 1
1 0
X
X’
© 2006
A
B
C
0 Volts 0 Volts 2.9 Volts
Department of Computing Science
The NOR Gate
A
A= 0V
B
B=0V
C= 0V
C
CMPUT 229
© 2006
A
B
C
0 Volts 0 Volts 2.9 Volts
0 Volts 2.9 Volts 0 Volts
Department of Computing Science
The NOR Gate
A
A= 0V
B
B=2.9V
C= 0V
C
CMPUT 229
© 2006
A
B
C
0 Volts 0 Volts 2.9 Volts
0 Volts 2.9 Volts 0 Volts
2.9 Volts 0 Volts 0 Volts
Department of Computing Science
The NOR Gate
A
A= 2.9V
B
B= 0V
C= 0V
C
CMPUT 229
© 2006
A
B
C
0 Volts 0 Volts 2.9 Volts
0 Volts 2.9 Volts 0 Volts
2.9 Volts 0 Volts 0 Volts
2.9 Volts 2.9 Volts 0 Volts
Department of Computing Science
The NOR Gate
A
A= 2.9V
B
B= 2.9V
A
0
0
1
1
B
0
1
0
1
C
1
0
0
0
C= 0V
C
X
Y
CMPUT 229
Z
© 2006
Department of Computing Science
What Logic Function this Circuit Implements?
A
0
0
1
1
A
B
B
0
1
0
1
C
1
0
0
0
D
0
1
1
1
1
C
D
This is an OR gate.
A
B
CMPUT 229
C=A+B
© 2006
Department of Computing Science
The AND Gate
A
0
0
1
1
A
B
C
D
B
0
1
0
1
C
1
1
1
0
1
A
B
CMPUT 229
D
0
0
0
1
C=A·B
© 2006
Department of Computing Science
Logic Functions
A
B
C=A·B
A
B
C=A+B
CMPUT 229
© 2006
Department of Computing Science
Logic Functions
INVERTER
X
X’
C=A·B
B
0
1
0
1
C
0
0
0
1
If A=1 AND B=1 then C=1
otherwise C=0
C=A+B
A
0
0
1
1
B
0
1
0
1
C
0
1
1
1
If A=1 OR B=1 then C=1
otherwise C=0
OR
A
B
If X=0 then X’=1
If X=1 then X’=0
A
0
0
1
1
AND
A
B
X’
1
0
X
0
1
CMPUT 229
© 2006
Department of Computing Science
NOR and NAND
Because these combination of gates are used often, there
are special symbols to represent them:
X
Y
Z
X
Y
Z
CMPUT 229

X
Y
Z

X
Y
Z
© 2006
Department of Computing Science
First DeMorgan’s Law
(X+Y)’ = X’Y’
X
Y
Z

X
Z
Y
The complement of the OR is equal the AND
of the complements.
X
0
0
1
1
Y
0
1
0
1
X+Y
0
1
1
1
(X+Y)’
1
0
0
0
CMPUT 229
X’
1
1
0
0
Y’
1
0
1
0
X’Y’
1
0
0
0
© 2006
Department of Computing Science
Decoders
– General decoder structure
– Typically n inputs, 2n outputs
– 2-to-4, 3-to-8, 4-to-16, etc.
CMPUT 229
© 2006
Department of Computing Science
Decoders
a
b
c
3-to-8
Line
Decoder
y0 = a’b’c’
y1 = a’b’c
y2 = a’bc’
y3 = a’bc
y4 = ab’c’
y5 = ab’c
y6 = abc’
y7 = abc
CMPUT 229
+
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
y0
1
0
0
0
0
0
0
0
y1
0
1
0
0
0
0
0
0
y2
0
0
1
0
0
0
0
0
y3
0
0
0
1
0
0
0
0
y4
0
0
0
0
1
0
0
0
y5
0
0
0
0
0
1
0
0
y6
0
0
0
0
0
0
1
0
y7
0
0
0
0
0
0
0
1
© 2006
Department of Computing Science
Binary 2-to-4 decoder
Note “x” (don’t care) notation.
CMPUT 229
© 2006
Department of Computing Science
2-to-4-decoder logic diagram
CMPUT 229
© 2006
Department of Computing Science
Instruction Decoder
COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED
CMPUT 229
Clements, pp. 86
© 2006
Department of Computing Science
The 74138 3-to-8 Decoder
COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED
CMPUT 229
Clements, pp. 86
© 2006
Department of Computing Science
Multiplexer
COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED
CMPUT 229
Clements, pp. 84
© 2006
Department of Computing Science
Multiplexer
COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED
CMPUT 229
Clements, pp. 85
© 2006
Department of Computing Science
Multiplexers
I0
I1
4-to-1
MUX
I2
I3
A
A
0
0
1
1
+
B
B
0
1
0
1
Z
I0
I1
I2
I3
Z
A’
B’
I0
A’
B
I1
Z
A
B’
I2
A
B
I3
CMPUT 229
© 2006
Department of Computing Science
Multiple 2-to-1 Multiplexers
COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED
CMPUT 229
Clements, pp. 84
© 2006