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Chalmers University of Technology
Power Estimation
FlexSoc Seminar Series – 2004-03-15
Daniel Eckerbert
[email protected]
FlexSoC Seminar Series – 2004-03-15
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Chalmers University of Technology
Outline
• Why power estimation?
• Power macromodeling
• Future directions for power estimation
Most pictures (non-Matlab-plots) are courtesy of Intel Corp.
FlexSoC Seminar Series – 2004-03-15
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Chalmers University of Technology
Why Power Estimation?
(Conference-Presentation Answer)
• Heat removal is expensive (fans, heat-sinks)
• Energy stored in battery is limited
• Power delivery is expensive (area,
reliability, verification, packaging)
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Chalmers University of Technology
Why Power Estimation?
(FlexSoC Answer)
• Compiler optimizations
• “Designing” range of chips for certain
applications
• ??? You tell me!
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Chalmers University of Technology
Power Reduction Techniques
• Activity reduction
• Supply voltage scaling
• Leakage reduction (cut-off techniques, stacking
etc)
But, by how much does the power of a specific
design needs to be reduced? And which power
mechnism constitutes a problem?
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Chalmers University of Technology
Power Dissipation Basics
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Chalmers University of Technology
From Where Does the
Power Increase Stem?
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Chalmers University of Technology
Increased Integration
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Chalmers University of Technology
Increased Integration
120 billion transistors
per wafer!!!
SRAM chips fabricated
on a 300mm wafer
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Chalmers University of Technology
Increased Density
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Chalmers University of Technology
Power Density
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Chalmers University of Technology
Heat Removal (die)
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Chalmers University of Technology
Heat Removal (package)
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Chalmers University of Technology
Power Macro Modeling
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Chalmers University of Technology
Architecture Level Power
Macromodeling à la Wattch
• P=0.1*Psw(αmax)+Psw(α,state)
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Chalmers University of Technology
What Do We Want from a
Power Estimation Methodology?
• Accurate
• Fast
• Provide information for power reduction
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Chalmers University of Technology
Levels of Power Estimation
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Chalmers University of Technology
Why Use Macro Models?
• Circuit simulations excessively time- and
memory-consuming
• Designers need to run long traces to
compare solutions (only possible using
macro models)
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Chalmers University of Technology
Estimation Tool Run-Times
Run-time
HSpice*
PowerMill *
Macro**
16b HanCarlson
8b Multiplier
12d14h
8h49m
(30x)
17h37m
(40x)
6m43s
(2700x / 80x)
9m42s
(4300x / 100x)
32b Multiplier
N/A
14d10h
2h2m
(N/A / 170x)
29d6h
* Highly
optimized code by team of software designers
** Highly unoptimized C++ code by one overworked
circuit designer
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Chalmers University of Technology
Precision
• Circuit simulations give full or close to full
precision (depending on extraction)
• Macro modeling can give range of precision
levels (with a maximum precision
determined by methodology)
• Macro model precision is limited by the
characterization
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Chalmers University of Technology
Power Estimation Flow
• Characterization
– Requires lower level simulations
– Has to support maximum precision
– One-time only, can afford to be slow
• Estimation
– Macro-model only
– Can support multiple levels of precision
– Frequently run, has to be fast
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Chalmers University of Technology
Characterization
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Chalmers University of Technology
Estimation
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Chalmers University of Technology
Switching Power
(Circuit Level)
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Chalmers University of Technology
Switching Power
(Early Power Macro Models)
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Chalmers University of Technology
Switching Power
(VLSI Research Group Style)
Equation-based 0→1 tracking, even for
intermediate nodes depending on accuracy
• Physical model based on nodal capacitances
and voltage swings
• Enables semi-automatic characterization
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Chalmers University of Technology
Short-Circuit Power
(Circuit Level)
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Chalmers University of Technology
Short-Circuit Power
(Macro Model)
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Chalmers University of Technology
Interconnect Modeling
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Chalmers University of Technology
CRC
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Chalmers University of Technology
RLC
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Chalmers University of Technology
Subthreshold-Leakage Power
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Chalmers University of Technology
Subthreshold-Leakage Power
(Circuit Level)
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Chalmers University of Technology
Subthreshold-Leakage Power
• Stacking effects
• Long settling times
• …?
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Chalmers University of Technology
Subthreshold-Leakage Power
(Macro Model)
• Equation-based model considering on- and
off-states of the transistors constituting the
gate
• Enables semi-automatic characterization
• Possible extensions for stacking
• Possible extensions for multiple clock-cycle
settling times
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Chalmers University of Technology
Gate-Leakage Power
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Chalmers University of Technology
Oxide Thickness
12 Å
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Chalmers University of Technology
Oxide Thickness
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Chalmers University of Technology
Gate-Leakage Power
(Circuit Level)
• Enough equations and theory to use up the
entire FlexSoC seminar series
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Chalmers University of Technology
Gate-Leakage Power
(Macro Model)
• Equation-based model considering on- and
off-states of the transistors constituting the
gate
• Enables semi-automatic characterization
• Complications include leakage paths
originating in one gate and ending up in
another gate
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Chalmers University of Technology
Separating Power
Dissipation Mechanisms
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Chalmers University of Technology
Leakage Power Increase
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Chalmers University of Technology
Active vs. Leakage Power
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Chalmers University of Technology
Separation of Mechanisms
(Rise- and Fall-Times)
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Chalmers University of Technology
Separation of Mechanisms
(Supply-Voltage Scaling)
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Chalmers University of Technology
Mismatch for Methodologies
without a Leakage Component
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Chalmers University of Technology
Mismatch for Methodologies without Leakage or
Dynamica Frequency and Supply Scaling
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Chalmers University of Technology
Added Complications
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Chalmers University of Technology
Complex Gates
• Most circuit-level models are only valid for
a single transistor or an inverter
• Macromodels have to be able to account for
large components, 32b multipliers etc
• Complexity increases super-linearly with
the number of transistors in the component
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Chalmers University of Technology
Non-Conforming Components
There are classes of components which do not
conform to the presented basic models:
• Clock generators
• Memories
• etc
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Chalmers University of Technology
Clock Generation (DLL)
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Chalmers University of Technology
Clock Generators (Delay Element)
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Chalmers University of Technology
Non-Linear Frequency Dependence
for Certain Types of Components
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Chalmers University of Technology
Dynamic Precision
• Different architectures might impose
different precision requirements for
different components (static during
estimation)
• Different operating modes might warrant
different need for precision (changes during
estimation)
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Chalmers University of Technology
Conclusions
• Power estimation is not simply about
averaging the current through the supplies
• Circuit simulation is too slow
• A lot of research is needed to enable highlevel power estimation for future designs:
some in mechanism modeling but more
importantly in the estimation framework
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Chalmers University of Technology
Power estimation is not as easy
as it looks
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