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EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Outline ■ Bubble Pushing ■ Compound Gates ■ Logical Effort Example ■ Input Ordering ■ Asymmetric Gates ■ Skewed Gates ■ Best P/N ratio ■ Pseudo-nMOS Logic ■ Dynamic Logic ■ Pass Transistor Logic 10.2 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example 1 1) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. D0 S Y D1 S 10.3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Bubble Pushing ■ Start with network of AND / OR gates ■ Convert to NAND / NOR + inverters ■ Push bubbles around to simplify logic ► Remember DeMorgan’s Law Y Y (a) (b) Y (c) 10.4 D Y (d) Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example 2 2) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. D0 S D1 S 10.5 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y Compound Gates ■ Logical Effort of compound gates unit inverter AOI21 YA Y A BC A Y A B C A A 2 1 Y AOI22 Y A BC D Y 4 B C A 2 B 2 4 4 C Y 1 Complex AOI A B C D Y A 4 B 4 C 4 D 4 A 2 C 2 B 2 D 2 Y Y A B C D E D E A B C Y B 6 C 6 A 3 D 6 E 6 E 2 A 2 D 2 2 C gA = 3/3 gA = 6/3 gA = gA = p = 3/3 gB = 6/3 gB = gB = gC = 5/3 gC = gC = p = 7/3 gD = gD = p= gE = p= 10.6 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis B Y 2 Compound Gates ■ Logical Effort of compound gates unit inverter AOI21 YA Y A BC A Y A B C A A 2 1 Y AOI22 Y A BC D Y 4 B C A 2 B 2 4 4 C Y 1 Complex AOI A B C D Y A 4 B 4 C 4 D 4 A 2 C 2 B 2 D 2 Y Y A B C D E D E A B C Y B 6 C 6 A 3 D 6 E 6 E 2 A 2 D 2 2 C B gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3 p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3 gC = 5/3 gC = 6/3 gC = 8/3 p = 7/3 gD = 6/3 gD = 8/3 p = 12/3 gE = 8/3 p = 16/3 10.7 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y 2 Example 3 ■ The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. D0 S Y D1 S D0 S D1 S H = 160 / 16 = 10 B=1 N=2 10.8 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y NAND Solution P 224 G (4 / 3) (4 / 3) 16 / 9 F GBH 160 / 9 fˆ N F 4.2 D0 S Y D1 S D Nfˆ P 12.4 10.9 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Compound Solution P 4 1 5 G (6 / 3) (1) 2 F GBH 20 fˆ N F 4.5 D0 S D1 S D Nfˆ P 14 10.10 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y Example 4 ■ Annotate your designs with transistor sizes that achieve this delay. 8 8 8 8 25 25 25 8 8 Y 25 10 10 10 10 24 6 6 12 6 6 Y 8 8 16 10.11 160 * (4/3) / 4.2 = 50 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 16 160 * 1 / 4.5 = 36 Input Order ■ Our parasitic delay model was too simple ► Calculate parasitic delay for Y falling ▼ If A arrives latest? 2 ▼ If B arrives latest? 2.33 2 10.12 2 A 2 B 2x Y 6C 2C Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Inner & Outer Inputs ■ Outer input is closest to rail (B) ■ Inner input is closest to output (A) ■ If input arrival time is known ► Connect latest input to inner terminal 10.13 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2 2 A 2 B 2 Y Asymmetric Gates ■ Asymmetric gates favor one input over another ■ Ex: suppose input A of a NAND gate is most critical ► Use smaller transistor on A (less capacitance) ► Boost size of noncritical input ► So total resistance is same A reset Y 2 A ■ gA = 10/9 ■ gB = 2 reset 2 Y 4/3 4 ■ gtotal = gA + gB = 28/9 ■ Asymmetric gate approaches g = 1 on critical input ■ But total logical effort goes up 10.14 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Symmetric Gates ■ Inputs can be made perfectly symmetric 10.15 2 2 A 1 1 B 1 1 Y Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Skewed Gates ■ Skewed gates favor one edge over another ■ Ex: suppose rising output of inverter is most critical ► Downsize noncritical nMOS transistor HI-skew inverter unskewed inverter (equal rise resistance) 2 A unskewed inverter (equal fall resistance) 2 Y 1/2 A 1 Y A 1 Y 1/2 ■ Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. ► gu = 2.5 / 3 = 5/6 ► gd = 2.5 / 1.5 = 5/3 10.16 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis HI- and LO-Skew ■ Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. ■ Skewed gates reduce size of noncritical transistors ► HI-skew gates favor rising output (small nMOS) ► LO-skew gates favor falling output (small pMOS) ■ Logical effort is smaller for favored direction ■ But larger for the other direction 10.17 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Catalog of Skewed Gates Inverter NAND2 2 unskewed 1 Y gu = 1 gd = 1 gavg = 1 A 2 B 2 2 HI-skew 1/2 Y gu = 5/6 gd = 5/3 gavg = 5/4 1 B 1 1 LO-skew 10.18 A 1 Y gu = 4/3 gd = 2/3 gavg = 1 2 B 2 4 1 1 B 4 A 4 1/2 gu = 1 gd = 2 gavg = 3/2 1 A A gu = 5/3 gd = 5/3 gavg = 5/3 Y Y 1 4 gu = 4/3 gd = 4/3 gavg = 4/3 2 A B Y Y 2 A 2 Y 2 A NOR2 1/2 B 2 A 2 gu = 3/2 gd = 3 gavg = 9/4 Y gu = 2 gd = 1 gavg = 3/2 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1 1 gu = 2 gd = 1 gavg = 3/2 Asymmetric Skew ■ Combine asymmetric and skewed gates ► Downsize noncritical transistor on unimportant input ► Reduces parasitic delay for critical input A reset Y 1 A reset 10.19 2 Y 4/3 4 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Best P/N Ratio ■ We have selected P/N ratio for unit rise and fall resistance (m = 2-3 for an inverter). ■ Alternative: choose ratio for least average delay ■ Ex: inverter ► Delay driving identical inverter P ► tpdf = (P+1) A ► tpdr = (P+1)(m/P) ► tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2 ► Differentiate tpd w.r.t. P ► Least delay for P = 10.20 m Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1 P/N Ratios ■ In general, best P/N ratio is sqrt of that giving equal delay. ► Only improves average delay slightly for inverters ► But significantly decreases area and power Inverter NAND2 2 fastest P/N ratio 10.21 A 1.414 Y 1 gu = 1.15 gd = 0.81 gavg = 0.98 NOR2 2 Y A 2 B 2 B 2 A 2 Y gu = 4/3 gd = 4/3 gavg = 4/3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1 1 gu = 2 gd = 1 gavg = 3/2 Observations ■ For speed: ► NAND vs. NOR ► Many simple stages vs. fewer high fan-in stages ► Latest-arriving input ■ For area and power: ► Many simple stages vs. fewer high fan-in stages 10.22 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis ■ What makes a circuit fast? -> tpd (C/I) DV ► low capacitance ► high current ► small swing ► I = C dV/dt B 4 A 4 ■ Logical effort is proportional to C/I ■ pMOS are the enemy! ► High capacitance for a given current ■ Can we take the pMOS capacitance off the input? ■ Various circuit families try to do this… 10.23 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y 1 1 Pseudo-nMOS ■ In the old days, nMOS processes had no pMOS ► Instead, use pull-up transistor that is always ON ■ In CMOS, use a pMOS that is always ON ► Ratio issue ► Make pMOS about ¼ effective strength of pulldown network 1.8 1.5 load P/2 1.2 P = 24 Ids Vout 0.9 Vout 16/2 Vin 0.6 P = 14 0.3 P=4 0 0 0.3 0.6 0.9 Vin 10.24 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 1.2 1.5 1.8 Pseudo-nMOS Gates ■ Design for unit current on output to compare with unit inverter. ■ pMOS fights nMOS Y inputs f Inverter Y A 10.25 NAND2 gu gd gavg pu pd pavg = = = = = = A B gu g Y gd avg pu pd pavg NOR2 = = = = = = Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis A B gu gd gavg Y pu pd pavg = = = = = = Pseudo-nMOS Gates ■ Design for unit current on output to compare with unit inverter. ■ pMOS fights nMOS Y inputs f Inverter 2/3 Y A 4/3 10.26 NAND2 gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9 A B gu 2/3 g Y gd avg 8/3 pu pd 8/3 pavg NOR2 = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9 2/3 A Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 4/3 B gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9 Dynamic Logic ■ Dynamic gates uses a clocked pMOS pullup ■ Two modes: precharge and evaluate 2 A Y 1 Static 2/3 Precharge 1 Y A 4/3 Pseudo-nMOS Y A Dynamic Evaluate Y 10.27 1 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Precharge The Foot ■ What if pulldown network is ON during precharge? ■ Use series evaluation transistor to prevent fight. precharge transistor Y Y inputs A Y inputs f f foot footed 10.28 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis unfooted Logical Effort Inverter unfooted NAND2 1 gd pd footed 2 2 10.29 2 B 2 gd pd = 2/3 = 3/3 1 Y gd pd = 2/3 = 3/3 1 A B 1 gd pd = 1/3 = 3/3 1 Y 1 Y A A = 1/3 = 2/3 1 Y 1 Y A NOR2 A 3 B 3 3 1 Y gd pd = 3/3 = 4/3 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis A 2 B 2 2 gd pd = 2/3 = 5/3 Monotonicity ■ Dynamic gates require monotonically rising inputs during evaluation ► 0 -> 0 ► 0 -> 1 ► 1 -> 1 A ► But not 1 -> 0 violates monotonicity during evaluation A Precharge Evaluate Precharge Y Output should rise but does not 10.30 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Monotonicity Woes ■ But dynamic gates produce monotonically falling outputs during evaluation ■ Illegal for one dynamic gate to drive another! A=1 A Y Precharge Evaluate Precharge X X X monotonically falls during evaluation Y Y should rise but cannot 10.31 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Domino Gates ■ Follow dynamic stage with inverting static gate ► Dynamic / static pair is called domino gate ► Produces monotonic outputs domino AND Precharge Evaluate Precharge W W X Y Z X A B C dynamic static NAND inverter Y Z A B 10.32 W X H C Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y H Z = A B X C Z Domino Optimizations ■ Each domino gate triggers next one, like a string of dominos toppling over ■ Gates evaluate sequentially but precharge in parallel ■ Thus evaluation is more critical than precharge ■ HI-skewed static stages can perform logic S0 S1 S2 S3 D0 D1 D2 D3 H Y 10.33 S4 S5 S6 S7 D4 D5 D6 D7 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Dual-Rail Domino ■ Domino only performs noninverting functions: ► AND, OR but not NAND, NOR, or XOR ■ Dual-rail domino solves this problem ► Takes true and complementary inputs ► Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged 0 1 ‘0’ 1 0 ‘1’ 1 1 invalid 10.34 Y_l inputs Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis f Y_h f Example: AND/NAND ■ Given A_h, A_l, B_h, B_l ■ Compute Y_h = AB, Y_l = AB ■ Pulldown networks are conduction complements Y_l A_h = A*B A_l B_l B_h 10.35 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Y_h = A*B Example: XOR/XNOR ■ Sometimes possible to share transistors Y_l = A xnor B A_h Y_h A_l A_l B_l B_h 10.36 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis A_h = A xor B Leakage ■ Dynamic node floats high during evaluation ► Transistors are leaky (IOFF 0) ► Dynamic value will leak away over time ► Formerly miliseconds, now nanoseconds ■ Use keeper to hold dynamic node ► Must be weak enough not to fight evaluation weak keeper A 1 k X H Y 2 2 10.37 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Charge Sharing ■ Dynamic gates suffer from charge sharing A Y CY x A Y B=0 Cx Charge sharing noise x CY Vx VY VDD C x CY 10.38 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Secondary Precharge ■ Solution: add secondary precharge transistors ► Typically need to precharge every other node ■ Big load capacitance CY helps as well Y A secondary precharge transistor x B 10.39 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Noise Sensitivity ■ Dynamic gates are very sensitive to noise ► Inputs: VIH Vtn ► Outputs: floating output susceptible noise ■ Noise sources ► Capacitive crosstalk ► Charge sharing ► Power supply noise ► Feedthrough noise ► And more! 10.40 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Power ■ Domino gates have high activity factors ► Output evaluates and precharges ▼ If output probability = 0.5, a = 0.5 – Output rises and falls on half the cycles ► Clocked transistors have a = 1 ■ Leads to very high power consumption 10.41 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Domino Summary ■ Domino logic is attractive for high-speed circuits ► 1.3 – 2x faster than static CMOS ► But many challenges: ▼ Monotonicity, leakage, charge sharing, noise ■ Widely used in high-performance microprocessors in 1990s when speed was king ■ Largely displaced by static CMOS now that power is the limiter ■ Still used in memories for area efficiency 10.42 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis