Download The Conventional Dual

The New Single-silicon TFTs Structure for Kinkcurrent Suppression with Symmetric Dual-Gate by
Three Split Floating N+ Zones
Supervised by Man Young Sung (Korea Univ.)
Dept. of Electrical Engineering, Korea Univ. Dae Yeon Lee
2
Contents
Introduction
Background
Proposal
Simulation & Results
Conclusion
Semiconductor & CAD Lab.
Dae Yeon Lee
3
Introduction

The Conventional Single-Gate TFT

The Conventional Dual-Gate TFT
* High On-current
* Low On-current
* High Electric Field at the Channel/Drain Junction
* Low Electric Field at the Channel/Drain Junction
* Kink-Effect
* Stable I-V Characteristic by Kink-Effect Suppression
Premature Breakdown !
High On-Current
+
Reduction of Kink-Effect
Goal is the Mixing of The Merit the each two TFTs
1. Kink-Effect Suppression
2. Improved On-Current
Semiconductor & CAD Lab.
Dae Yeon Lee
4
Back Ground

Lowering the Electric Field by having Dual-Gate Structure
Lowering the Impact Ionization at the
Channel/Drain Junction
Lowering the Generated Holes flowed to
Source/Channel Junction
Defense
Floating N+ region recombines with
the Holes
PBT action
Parasitic Bipolar
Transistor
Defense the lowering the Electrostatic Potential
Barrier at the Source/Channel Junction by the
Holes
Proposed TFT structure achieved the reduction of
the Kink-Effect so that stable Drain Current in the
Saturation Region
Semiconductor & CAD Lab.
Dae Yeon Lee
5
Proposal

The Dual-Gate TFT with Floating N+ channel
- Off-Set Region
Electrons inject at the Forward Bias
3um
Mo
Lowering the Electric Field
Middle N+ region length < 1.51 um
Gate
400nm
Mo
Gate
700nm
100nm
Source
N+
P
1um
oxide
N+
1.65um
P
N+
1.65um
P
0.7um
2um
N+
2um
Drain
P
1um
400nm
N+
110nm
16um
Total channel length=10um
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Dae Yeon Lee
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
Design Rules
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Dae Yeon Lee
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Simulation & Results





Electrostatic Potential
Hole concentration
Electric Field
Drain Current – Drain Voltage
Output Characteristics
Output Conductance
Semiconductor & CAD Lab.
Dae Yeon Lee
8

Electrostatic Potential
VG = 7 V, VD = 12 V
Conventional
Conventional
Proposed
Single-gate TFT
Dual-gate TFT
Dual-gate TFT

Lowering potential barrier at the source causes the kink effect.

Proposed TFT’s potential barrier enhanced the potential barrier 5 times than
Single - gate TFT and enhanced 18 % that of conventional dual-gate TFT.
Semiconductor & CAD Lab.
Dae Yeon Lee
9

Electrostatic Potential (Zoom In)
VG = 7 V, VD = 12 V
Channel
Source

The channel region starts from 4.3 um point

The Potential Barrier value for the each TFTs Value is 0.5 V, 2.3 V, 2.8 V at a 5 um
point which starts floating n+ region
Semiconductor & CAD Lab.
Dae Yeon Lee
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
Hole Concentration
VG = 7 V, VD = 12 V
> 1017

Conventional
Conventional
Proposed
Single-gate TFT
Dual-gate TFT
Dual-gate TFT
High Electric field at Drain Junction causes Impact Ionization so that holes flow to
the source junction through channel -> PBT action

Floating N+ regions recombine with holes so that hole concentration at the source
junction can be reduce.
Semiconductor & CAD Lab.
Dae Yeon Lee
11

Hole Concentration (Zoom In)
Source


VG = 7 V, VD = 12 V
Channel
The channel region starts from 4.3 um point
The Hole concentration value for the each TFTs Value is 1017 /cm3, 101 /cm3,
10-1 /cm3 at a 5 um point which starts floating n+ region
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Dae Yeon Lee
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
Electric Field
VG = 7 V, VD = 12 V
Conventional
Conventional
Proposed
Single-gate TFT
Dual-gate TFT
Dual-gate TFT

High Electric field at Drain Junction causes kink effect.

The usual approach to reduce this effect is to limit the impact ionization
contribution decreasing the electric field at the drain junction.
Semiconductor & CAD Lab.
Dae Yeon Lee
13

Electric Field (Zoom In)
VG = 7 V, VD = 12 V
Channel Drain

The channel region starts from 12.9 um point

The electric field value of each TFT is approximately 105 V, 2.8×102 V, and
2.9×102 V.
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Dae Yeon Lee
14

Drain Current – Drain Voltage Output Characteristics
1.611 mA
0.870 mA
0.522 mA
VG = 7 V, VD = 12 V
The
on-current of the proposed dual-gate TFT is 0.870 mA while that of the
conventional dual-gate TFT is 0.522 mA

This result shows a 67 % enhancement in on-current
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Dae Yeon Lee
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
Drain Current – Drain Voltage Output Characteristics
Conventional
Single-gate TFT
Conventional
Dual-gate TFT
Proposed
Dual-gate TFT
VG=5 V
VD=10V
0.824 mA
0.325 mA
0.508 mA
VG=5 V
VD=12V
1.078 mA
0.330 mA
0.522 mA
VG=7 V
VD=10V
1.257 mA
0.508 mA
0.862 mA
VG=7 V
VD=12V
1.611 mA
0.522 mA
0.870 mA
W/L = 2
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Dae Yeon Lee
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
Drain Current – Drain Voltage Output Characteristics

The on-current of the proposed dual – gate TFT
at different gate voltage
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Dae Yeon Lee
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
Output Conductance Characteristics
VG = 7 V, VD = 12 V
Kink starting point

Reduction of the Output conductance means the reduction of the kink effect
so that we can get a stable drain current in the saturation region.

The output conductance of the conventional single-gate increases about 8.3 V.
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Dae Yeon Lee
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Conclusion

Lowering the High electric Field at the Drain junction by
Dual – Gate TFT structure

Improved Electrostatic Potential

Reduction of the Hole concentration by the holes recombine with
the Floating N+ region in the channel region

On-Current is 0.870 mA in the saturation region while that of the
conventional dual – gate TFT is 0.522 mA at VG = 7 , VD = 12 V
 A stable
Output Conductance is accomplished by the reduction
of the kink effect
Semiconductor & CAD Lab.
Dae Yeon Lee