Download Swientek-Torino2004

Multichannel integrated circuits
for digital X-ray imaging
with energy windowing
Krzysztof Świentek
Department of Nuclear Electronics
FPNT, AGH Kraków
[email protected]
2004
Content
• Introduction – multichannel ASICs
• Noise in MOS transistors
• Crosstalk in mixed–mode integrated circuits
• Random matching
• RX64DTH – digital imaging using silicon detectors
• Measurements results – chip tutorial
• Summary
2004
Introduction  multichannel ASIC
SET OF SENSORS ( silicon strip detector)
Input signals - small amplitude (Qin = 1400 el)
- stochastic character (amplitude, time)
MULTICHANNEL INTEGRATED CIRCUITS (analogue & digital blocks)
6.5 mm
LIMITS:
power & area
LOW LEVEL
OF NOISE
RX64DTH
UNIFORMITY OF
PARAMETERS
CROSSTALK
digital  analogue
2004
Noise in MOS transistors
1. Thermal noise of channel
saturation
linear
dith2 8
 kTgm
df
3
dith2
 4kTgds
df
Simulations (HSPICE)
NLEV=3
dith2 8kT
W
1  a  a2

 Cox VGS  VT 
GDSNIO
df
3
L
1 a
BSIM3v3 (NIMOD=2)
dith2 4kTeff

Qinv
df
L2eff
Measurments – short channel effects (2-10x):
( velocity saturation, hot electrons)
2. Flicker noise
Simulations (HSPICE)
NLEV=2, 3
di12/ f
KF g m2
1

df
Cox Weff Leff f AF
BSIM3v3 (NIMOD=2)
Measurments – short channel effects
( hot electrons, RST noise)
2004
CROSSTALK
DIGITAL
BLOCKS
GENERATION
ANALOG
BLOCKS
SILICON SUBSTRATE
TRANSFER
EFFECT
Transfer:
– common supply lines: parasitic inductance and resistance (Vind=LdI/dt)
– common substrate: (substrateepi, VT=f(VSB), gmb)
Effects for analogue blocks: switching noise, oscillation etc.
Minimisation:
– reducing the noise generation,
– increasing the immunity of analogue part,
– isolation techniques.
2004
MATCHING - identically design devices have different parameters
P=P1-P2 (P/P)
L
L
AP2
 P  
 SP2 D 2
WL
2
W
W
Number of cases
RANDOM MATCHING
P/P [%]
D
For MOS transistors: VT0 , , 
VT0   MS  2  F 
4q s  F N B
Qox

Cox
Cox
CMOS 0.7m - (VT0)
NMOS
PMOS
W/L=2m/0.7m
9.72 mV
19.43 mV
W/L=1500m/1.5m
0.31 mV
0.63 mV
   Cox
W
L

2q s N B
Cox
2004
1. Matching  bias condition
differences: VT, , R
a)
a)
Vosr
b)
VDD
R1
V  V  R  
  VT  GS T  

 R
2
 

R2
OUT1
IREF
OUT2
IN1
IN2
M1
M2
b)
I DS
2


VT 
I DS
VGS  VT

VDD
IBIAS
M0
IDS1
IDS2
M1
M2
2. Reduce sensitivity - proper configuration (Kv Ci/Cj)
3. Monte-Carlo analysis using
HSPICE
4. Symmetry in layout
(matching data for given technology)
– common centroid geometry, unit cells,
– bias, temperature, orientation,
– surrounding, metal coverage
2004
X-ray imaging using silicon strip detectors
Key system issues:
– fully parallel signal processing for all channels.
– only binary information (yes/no) is extracted from each strip.
– data from each channel must be stored in the local buffer for
the whole measurement period.
Signal 10x smaller
Stochastic
X-rays
current pulses
High Energy Physics
100 m
data, control
Silicon strip detector
PC
computer
Integrated circuit
2004
RX64DTH - fully integrated 64-channel chip (CMOS 0.8 m process)
RX64DTH consists of:
– 64 front-end channels (preamplifier, shaper, two discriminators)
– 128 pseudo-random counters (20-bit)
– internal DACs: two 8-bit threshold setting and and three 5-bit
for bias
– internal calibration circuit (square wave 1mV-30 mV)
– control logic
– I/O circuit (interface to external bus)
37006500 m2
2004
Single analogue channel
V
VT-HIGH
0
V
V
VT-LOW
C3
t
t
t
Tp
C2
Shaper
1
C5
0
Preamplifier
Discriminators 
Key design issues:
– low noise (ENC  200 el. rms, sensor )
– low power (3-5 mW/channel)
– relatively fast shaping (Tp = 0.5  1s)
– uniformity from channel to channel (gain, offset, noise)
– immunity to switching noise
2004
Preamplifier
&
shaper
V
V
t
t
SENSOR:
Cdet
Idet
Rbias
Tp
LIMITATIONS
Minimum of noise (transistor dimensions, bias)
1. POWER
dvn2
b
a
df
f
Fv Cin2
ENC  a
 bFvf Cin2  cFiTp
Tp
din2
c
df
3. SENSOR
4. PSRR, stability, matching.
Hand calculation
K 1 1
dvn2 8
1
 kT
 2f
df
3 gm1 Cox W1L1 f
2
n
di
4kT 4kT
 2qI DET 

df
Rbias R fed
M1: 500/1
2. PEAKING TIME
M5: 2/120
Simulation
HSPICE
Measurements
(bias, temp., Tp)
DAC currents
Other
transistors
M4: 100/10
–
IFED
– IFEDSH
– ICAS
Id = 500 A
2004
ENC
versus
Peaking Time
V
t
Noise types
Tp
ENC – total noise
ENCW – white voltage noise
ENCf – 1/f voltage noise
ENCi – white current noise
TP [s]
Peaking time TP
• Optimal
 the lowest noise
• Fast Front-end
 increasing noise
2004
Discriminator – offsets, crosstalk
1
V
0
VT-HIGH
VT-LOW
t
Tp
1
• AC coupling
• differential stage (CMRR)
• hysteresis
0
• power supply lines, guard
rings
2004
Pseudo-random counters
– 20 bit counters (large dynamic range of the image)
– small layout area (only 8 transistor per bit)
– 128 counters are grouped in the 8 blocks of 16 counters each
(8 bit I/O bus to minimize the dead time)
2004
Functionality & testability
Calibration circuits: Qinj=CtVcal (500 el - 13000 el)
Internal DACs: threshold setting, gain, peaking time
Command code
Action
000
SetGateStatus
001
ReadoutDestructive
010
ReadoutNonDestructive
011
CalibrationPulseLong
100
CalibrationPulseShort
101
CounterPulse
110
LoadDac
111
Unused code
I/O circuits:
2 x threshold 8-bit
3 x bias
5-bit
1 x calibration 4-bit
6 dacs
• LVDS standard (command, clock)
• 8-bit data bus (tristate),
• 3-bit address (up to 8 chips)
2004
LAYOUT - floor plan, bias lines, pads
Floor plan
2
– preamplifier & shaper
– discriminators 3
– counters & IOs 4
– digital outputs 12
– control logic 5
– calibration 6
– bias DACs 7
Isolation techniques
8
– reduce inductance (separate
bias line,pads), 9 10 11 14
– floor plan, bias lines
– keep “clean” substrate – LVDS
13
– RC filters
– guard rings, shielding
Digital
guard ring
Analog
guard ring
Digital
ground
Middle
ring
Analog
ground
2004
Window – threshold DAC’s
0,5
800
0,4
0,3
600
0,2
500
0,1
400
0,0
300
-0,1
Error [LSB]
Voltage [mV]
700
-0,2
200
-0,3
100
-0,4
0
-0,5
0
50
100
150
200
250
Dacvalue
value [LSB]
Dac
[LSB]
– two independent DACs
– common centroid matrix
– mixed matrices
– matching problem
– need software correction
20
6
5
4
10
3
2
5
1
0
3,67eV/el
Difference between
DAC HIGH and LOW
7 LSB
0
0
Silicon:
Difference [LSB]
[LSB]
Difference
[mV]
Difference
Difference
[mV]
15
50
100
150
200
250
Dac value [LSB]
Dac value
[LSB]
2004
Noise
IFED
[LSB]
IFED
SH
[LSB]
ICAS
[LSB]
32
32
32
32
32
32
Temp.
versus
ICAS & Temp
Gain
[V/el]
()
Offset
[mV]
()
ENC
[el. rms]
8 keV
ENC
[el. rms]
20 keV
ENC
[el. rms]
Cal 10
room
57.63
(0.34)
-9.23
(1.91)
248
(6.1)
232
(7.7)
232
(24)
32
room
56.79
(0.34)
-11.84
(1.91)
251
(6.1)
234
(8.5)
32
40
room
32
32
48
room
32
32
56
room
VTH = 255
VTL = scan
VTH = scan
VTL = 255
219
(24)
56.30
(0.37)
-11.50
(1.96)
233
(7.5)
217
(7.3)
213
(15)
Source Pu238 + Cu
203
(13)
32
32
56
25°
Vdet = 130 V
191
32
32
63
25°
Vdd
= 4.0 V
185
32
32
63
20°
Vddd = 4.0 V
175
32
32
63
18°
Peltier element for temp.
163
Controled
Temp.
2004
Noise
versus
IFED
IFED
[LSB]
IFEDSH
[LSB]
ICAS
[LSB]
Temp.
Gain
[V/el]
()
Offset
[mV]
()
ENC
[el. rms]
8 keV
ENC
[el. rms]
20 keV
24
32
63
20°
54.86
(0.39)
-17.62
(1.33)
198.9
(5.1)
205.9
(16.7)
32
32
63
20°
54.85
(0.44)
-17.85
(1.09)
203.1
(6.6)
201.5
(8.22)
40
32
63
20°
54.86
(0.45)
-17.55
(1.26)
220.7
(8.5)
213.7
(9.47)
48
32
63
20°
54.84
(0.49)
-16.96
(1.30)
238.2
(9.2)
228.6
(9.46)
– gain & offset const
– window is 5 LSB
– Peltier element
}
fast
noise
increasing
pin-holes in detector  leakeage current  dead channels because
out of operating point
increase IFED but ...
rescue
2004
Simulation: TP & Gain as a function of IFEDSH
Impulse height
shaper

output
TP
• TP = 0.7 – 1 s
• Impulse fall ends  4 s  200 kHz
2004
Gain, Offset & Noise
versus
IFEDSH
– window is 5 LSB
IFED
[LSB]
IFEDSH
[LSB]
ICAS
[LSB]
Temp.
Gain
[V/el]
()
Offset
[mV]
()
ENC
[el. rms]
20 keV
32
16
63
20°
80.54
(0.57)
-0.8
(0.9)
177.5
(4.91)
32
24
63
20°
63.74
(0.52)
-11.68
(1.11)
197.6
(8.69)
54.85
(0.44)
-17.85
(1.09)
201.5
(8.22)
32
32
63
20°
32
40
63
20°
50.2
(0.36)
-20.59
(1.24)
206.5
(9.42)
32
48
63
20°
47.64
(0.35)
-21.67
(1.39)
209.9
(8.92)
32
63
63
20°
45.52
(0.32)
-22.82
(1.22)
210.7
(9.36)
– Peltier element
max (slow)
peaking
time
TP
min (fast)
2004
Summary
1.
Multichannel mix-mode ASIC :
— critical parameters connected together
— looking for a golden solution
2.
Software corrections :
— DACs problem
— differences between the chips
3.
Noise controling :
IFED
– better detector  lower noise
ICAS
– the highier the beter (cooling ?)
IFEDSH – high gain gives low noise and speed
4.
To do – measurements
— speed
— uniformity in 6-chip module
2004