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Rad-Hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Marlon Barbero – Centre de Physique des Particules de Marseille [email protected] Genova visit / December 16th 2013 ATLAS tracker upgrade plan New insertable b-layer (IBL) New Al beam pipe New pixel services Fast TracKing (FTK) for level2 trigger All new tracker (baseline: long strips /short strips / pixels) Possible level1 tracker Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 2 HL-LHC environment challenge • HL-LHC targets: – 14TeV; Luminosity: 5.1034 cm-2.s-1 / 3000 fb-1 in ~7 years • Consequences for trackers: – High radiation for the innermost layers (~5cm): • ~1.1016 neq.cm-2 / ~1GRad rad-hardness! (note: ~50-100MRad at 25cm) – High occupancy: • cope with of order <140> pile-up events / bunch-crossing high granularity! fast! – Huge surface to cover: • of order 200m2 reduction in costs! Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 3 Using Hybrid Detectors • Hybrid detectors: – n-in-n or n-in-p with reduced drift distance (3D or thin silicon). – DSM rad-hard IC (a la IBL FE-I4 -130nm- or reduced feature size 65nm?). – Valid option: should work (after development). – Drawback: 1- Price of hybridization / of non-standard sensors (yield?) and for a large area. 2- Will stay rather thick. 3- High bias voltage. 4- Deep charge collection leads to difficult 2-track separation in boosted jets. Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 4 Principle of HV-CMOS process • An n-well in p-substrate diode, populated with CMOS (first stage amplifier or more complex). CMOS! e.g. 1st stage amplifier n-well in p-substrate diode n-well biasing depletion zone around nwell: charge collected by drift resist~10Ω.cm Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 5 ATLAS HV-CMOS Collaboration • Bonn University: M. Backhaus, L.Gonella, T. Hemperek, F. Hügging, H. Krüger, T. Obermann, N. Wermes. • CERN: M. Capeans, S. Feigl, M. Nessi, H. Pernegger, B. Ristic. • CPPM: M. Barbero, F. Bompard, P. Breugnon, JC. Clemens, D. Fougeron, J. Liu, P.Pangaud, A. Rozanov. • Geneva University: D. Ferrere, S. Gonzalez-Sevilla, G. Iacobucci, A. Miucci, D. Muenstermann. • Goettingen University: M. George, J. Grosse-Knetter, A. Quadt, J. Rieger, J. Weingarten. • Glasgow University: R. Bates, A. Blue, C. Butter, D. Hynds. • Heidelberg University: I. Peric (original idea). • LBNL: M. Garcia-Sciveres. Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 6 Process Main Characteristics • CMOS electronics inside deep n-well. • Negatively biased substrate leads to ~8-10μm depletion zone charge collection by drift. • Small feature size + relatively low complexity of in-pixel logic small pixel. • 1st stage signal amplification on-sensor (low capacitance low noise). • Featuring: 1- electronics rad-hard (DSM technology). 2- sensor rad-hard (small depletion depth, small ΔNeff). 3- low price (standard CMOS process). 4- low material budget (can be thinned down). 5- low maximum bias voltage (moderate substrate resistivity). 6- fast (electronics on sensor). 7- good granularity (1st prototype 33×125μm2, can go down). • HV2FEI4p1/-p2 in AMS180nm HV-CMOS. Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 7 HV2FEI4 series • • • • • • -p1: Proof of principle. -p2: Rad-hardness enhanced. 2.2×4.4 mm2. 60columns×24rows. pixels: 33×125μm2. pads to realize various operation modes: IO for CCPD strip pads pixel array w. transmission pads – Standalone measurement possible. – CCPD: Capacitively coupled to pixel IC. IO for strips – Bonded to strip readout IC. Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 8 Readout -a la strips• Readout: use HV-CMOS sensor in combination with existing powerful IC by connecting HV-CMOS pixels in various ways. • e.g. pixels can be summed up as “virtual strips”, with hit position encoded as pulse height. 180 160 140 120 Counts 100 80 Pixel hit map from strip information (note the shadow of a wire) 60 40 20 0 -20 0,0 0,5 1,0 1,5 2,0 Measured analog address [V] Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 9 Readout -with larger pixels• Combine 3 pixels together to fit one FE-I4 pixel (50×250μm2), with HVCMOS pixels encoded by pulse height. • Capacitive coupling OK: gluing! (perspective to avoid bump-bonding?) The tiny HV2FEI4p1 prototype glued on the large FE-I4 Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 10 HV2FEI4p1 on FEI4 • 90Sr-source. • Readout through FE-I4. • kHz rate recorded! Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 11 Sub-pixel encoding principle unirradiated sensor • Works on single pixel cells. • Sub-addresses well separated in ToT histo. Sub-pixel 1 Sub-pixel 2 3 sub-pixels on Three values for the addresses decoded by Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 the FE-I4 pixel Sub-pixel 3 12 HV2FEI4p1 • Recorded routinely 90Sr and 55Fe spectra. Discri • Degradation at 80MRad proton irradiation (dead at 200MRad!) Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 13 Bulk damage • Small depletion depth + Neff > 1014.cm-3 bulk rad-hard? • Non-ionizing radiation at neutron source (Ljubljana) to occupancy in 1.1016 neq.cm-2. No source leakage current increase (as expected) 10 minutes With 90Sr sensor works at room T after 1016 neq.cm-2. (scintillator trigger used) Note: 30 days annealing at room temp Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 14 TID issue HV2FEI4p2 • Few pixel flavors with enhanced rad-hardness: guard rings, circular transistors… (different pixel types lead to different gains -expected-). 55Fe spectra, unirradiated “rad-hard” “normal” different gains Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 15 TID issue HV2FEI4p2 • After 862 MRad Xray (annealing included 2h at 70C each 100MRad), after parameter retuning, amplifier gain loss recovered to 90% of initial value Relative preampli amplitude variation as function of dose Recovery at 862 MRad (NOT 900MRad) Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 16 Conclusion • Principle: Firmly established. Various types of readout demonstrated, among which capacitive coupling through gluing to FE-I4. • Prospects for: Small pixels, less material, cheaper, large area… • Need further studies on radiation hardness, but positive indications of radiation tolerance. • Need efficiency / spatial resolution studies test beam. • Need optimization to establish geometry & architecture. • Discussion on new larger size prototype to realize currently on-going. Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 17 Outlook • Hybrid solution vs monolithic for future trackers? 65nm vs HVCMOS? • Our collaboration has started to look into other processes: Super Contact M1 M2 M3 M4 M5 T3-MAPS (LBNL) IBM 130nm M5 M4 M3 M2 M1 M M 6 6 Bond Interface Tie r2 sensor Tier 1 (thinne d wafer) Back Side Metal Super Contact GFMAPS (CPPM) GF 130nm Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 1640 electrons (assuming collected by one pixel) DMAPS (Bonn) ESPROS 150nm 18 BACKUP • BACKUP Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 19 New monolithic sensors on a fully isolated substrate Spectrum of Fe55 (X-ray) and Sr90 (e-), obtained from a 10mX10m single pixel. We have exploited a new CMOS substrate isolation implant to implement a monolithic radiation detector. Because the substrate is completely junction-isolated from the active wells, it can be biased at larger negative voltages than would be possible in a standard process. This not only permits true 100% fill factor but also improves the sensor performance. Preliminary results will be shown. 20 Outlook another 3D approach • We submitted on June 2013 a new HV2FEI4 version in GlobalFoundries 0.13µm BCDLite technology. The chip is 100% compatible with the HV2FEI4 chip, and could be easily tested. Despite some small failures, the chip works Back Side Metal at -30V sensor Tier 1 (thinne d wafer) Super Contact M5 M4 M3 M2 M1 M6 M6 Bond Interface Tie r2 M1 M2 M3 M4 M5 Super Contact • The HV2FEI4 could be use on a complex and advanced monolithic 3D chip, including analog sensor and digital post-processing parts Marlon Barbero, Genova visit to CPPM, Dec. 16th 2013 21 EPCB01 – Depleted monolithic pixel chip Features: Technology: ESPROS Feature size: CMOS 150 nm High resistive N-type bulk (~ 2 kΩ cm) High voltage at sensor domain possible (~ 10 V) Full depletion can be achieved P-type well to integrate CMOS electronics 6 metal layers Chip is thinned down to 50 µm New Physicist’s dream?? 17th September 2013, Future Pixel FE meeting 22 Source scan Fe55 Fe55 used for calibration of Sr90 plot Sr90 MPV ~2400 electrons (~ 4200 electrons expected for ~ 50 µm silicon) → rest of the charge is collected by other pixels (clustering) 17th September 2013, Future Pixel FE meeting 23