Download CMOS Inverter

CMOS Inverter:
VDD
Vin
Vout
CL
CMOS Inverter:
Steady State Response
VDD
VDD
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Rp
Vout = 1
Vout = 0
Rn
Vin = 0
Vin = V DD
CMOS Properties

Full rail-to-rail swing  high noise margins

Logic levels not dependent upon the relative device sizes 
transistors can be minimum size  ratioless

Always a path to Vdd or GND in steady state  low
output impedance (output resistance in k range) 
large fan-out (albeit with degraded performance)

Extremely high input resistance (gate of MOS transistor
is near perfect insulator)  nearly zero steady-state
input current

No direct path steady-state between power and ground
 no static power dissipation

Propagation delay function of load capacitance and
resistance of transistors
Review: Short Channel I-V Plot (NMOS)
X 10-4
2.5
VGS = 2.5V
2
VGS = 2.0V
1.5
1
VGS = 1.5V
0.5
VGS = 1.0V
0
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
Review: Short Channel I-V Plot (PMOS)

All polarities of all voltages and currents are reversed
-2
VDS (V)
-1
0
0
VGS = -1.0V
-0.2
VGS = -1.5V
-0.4
-0.6
VGS = -2.0V
-0.8
VGS = -2.5V
-1 X 10-4
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
Transforming PMOS I-V Lines

Want common coordinate set Vin, Vout, and IDn
IDn
IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
VGSp = -1
VGSp = -2.5
Mirror around x-axis
Vin = VDD + VGSp
IDn = -IDp
Horiz. shift over VDD
Vout = VDD + VDSp
CMOS Inverter Load Lines
PMOS
2.5
NMOS
X 10-4
Vin = 0V
Vin = 2.5V
2
Vin = 0.5V
Vin = 2.0V
1.5
Vin = 1.0V 1
Vin = 2V
0.5
Vin = 1V
Vin = 1.5V
Vin = 1.5V
Vin = 0.5V
Vin = 1.5V
Vin = 1.0V
Vin = 2.0V
Vin = 0.5V
0
Vin = 2.5V 0
0.5
1
1.5
Vout (V)
2
2.5 Vin = 0V
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
CMOS Inverter VTC
NMOS off
PMOS res
2.5
NMOS sat
PMOS res
Vout (V)
2
1.5
NMOS sat
PMOS sat
1
NMOS res
PMOS sat
0.5
NMOS res
PMOS off
0
0
0.5
1
1.5
Vin (V)
2
2.5
CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
VDD
Rp
Vout
Vout
CL
Vin = 0
CL
Rn
Vin = V DD
 Gate response time is determined by the time to charge CL
through Rp (discharge CL through Rn)
Relative Transistor Sizing

When designing static CMOS circuits,
balance the driving strengths of the
transistors by making the PMOS section
wider than the NMOS section to


maximize the noise margins and
obtain symmetrical characteristics
Switching Threshold

VM where Vin = Vout (both PMOS and NMOS in saturation
since VDS = VGS)
VM  rVDD/(1 + r) where r = kpVDSATp/knVDSATn

Switching threshold set by the ratio r, which compares
the relative driving strengths of the PMOS and NMOS
transistors

Want VM = VDD/2 (to have comparable high and low noise
margins), so want r  1
(W/L)p
=
kn’VDSATn(VM-VTn-VDSATn/2)
(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)
Switch Threshold Example

In our generic 0.25 micron CMOS process, using the
process parameters from slide L03.25, a VDD = 2.5V, and
a minimum size NMOS device ((W/L)n of 1.5)
NMOS
PMOS
VT0(V)
0.43
-0.4
(V0.5)
0.4
-0.4
VDSAT(V)
0.63
-1
k’(A/V2)
115 x 10-6
-30 x 10-6
(V-1)
0.06
-0.1
(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)
=
(W/L)n
x
-30 x
10-6
x
-1.0
(1.25 – 0.4 – 1.0/2)
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
= 3.5
Simulated Inverter VM
VM is relatively
insensitive to variations in
device ratio

1.5
1.4
1.3
setting the ratio to 3, 2.5
and 2 gives VM’s of 1.22V,
1.18V, and 1.13V

1.2
1.1
Increasing the width of
the PMOS moves VM
towards VDD

1
0.9
0.8
0.1
1
(W/L)p/(W/L)n
Note: x-axis is semilog
~3.4
10
Increasing the width of
the NMOS moves VM
toward GND

Noise Margins Determining VIH and VIL
By definition, VIH and VIL are
where dVout/dVin = -1 (= gain)
3
VOH = VDD
NMH = VDD - VIH
NML = VIL - GND
2
VM
Approximating:
VIH = VM - VM /g
VIL = VM + (VDD - VM )/g
1
VOL = GND0
VIL
Vin VIH
A piece-wise linear
approximation of VTC
So high gain in the transition
region is very desirable
CMOS Inverter VTC from Simulation
0.25um, (W/L)p/(W/L)n = 3.4
(W/L)n = 1.5 (min size)
VDD = 2.5V
2.5
Vout (V)
2
VM  1.25V, g = -27.5
1.5
VIL = 1.2V, VIH = 1.3V
NML = NMH = 1.2
(actual values are
VIL = 1.03V, VIH = 1.45V
NML = 1.03V & NMH = 1.05V)
1
0.5
0
0
0.5
1
Vin (V)
1.5
2
2.5
Output resistance
low-output = 2.4k
high-output = 3.3k
Gain Determinates
Vin
0
0
-2
-4
-6
-8
0.5
1
1.5
2
Gain is a strong function of the
slopes of the currents in the
saturation region, for Vin = VM
(1+r)
g  ---------------------------------(VM-VTn-VDSATn/2)(n - p )
-10
-12
-14
-16
-18
Determined by technology
parameters, especially channel
length modulation (). Only
designer influence through
supply voltage and VM (transistor
sizing).
Impact of Process Variation on VTC Curve
2.5
Good PMOS
Bad NMOS
Vout (V)
2
1.5
Nominal
1
Bad PMOS
Good NMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
Process variations (mostly) cause a shift in the switching threshold
Scaling the Supply Voltage
2.5
0.2
2
Vout (V)
Vout (V)
0.15
1.5
1
0.1
0.05
0.5
Gain=-1
0
0
0
0.5
1
1.5
Vin (V)
Device threshold voltages are
kept (virtually) constant
2
2.5
0
0.05
0.1
0.15
Vin (V)
Device threshold voltages are
kept (virtually) constant
0.2
The VTC for a 180nm Process