Download Pass Transistor Logic, Standard Cell Layout Methodology

Notices
•You have 18 more days to complete your final
project!
•Collaborate with each other (NOT Copy!!)
•Presentations will be held on March 7 (Tuesday)
and March 9 (Thursday) In Rm. 301 During Lab
Hours
•Magiboard, Projector, Notebook PC will be
available to you
•Use the Color Printer!
EE415 VLSI Design
COMBINATIONAL
LOGIC
Complete Reading 4.2
Start Reading 4.3
(dynamic CMOS)
EE415 VLSI Design
Fast Complex Gate - Design
Techniques
•Transistor Sizing
•Minimize tp(worst-case)
•Progressive Sizing
•As long as fan-out capacitance dominates
•Transistor Ordering
•Minimize Critical Path
•Improved Logic Design
•Minimize fan-in
EE415 VLSI Design
Fast Complex Gate - Design
Techniques
•Buffering
•Isolate fan-in from fan-out
•Ratioed Logic (NMOS, Pseudo-NMOS)
•To reduce the # transistors
•Adaptive Load
•Reduce power dissipation during standby
EE415 VLSI Design
Fast Complex Gate - Design
Techniques
•Dual Cascode Voltage Switch Logic (DCVSL)
•No static power dissipation!
•More complex (=> more area)
•Pass Transistor Logic
•N transistors
•No Static power consumption
EE415 VLSI Design
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
EE415 VLSI Design
B
B
NMOS-only switch
C=5V
C=5V
M2
A=5V
A=5V
B
B
Mn
CL
M1
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes
static power consumption
EE415 VLSI Design
Solution 1: Transmission Gate
C
A
C
A
B
B
C
C
C=5 V
A=5V
B
CL
C=0V
EE415 VLSI Design
Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
R (Ohm)
20000.0
Rp
10000.0
0.0
0.0
Req
1.0
2.0
3.0
Vout
EE415 VLSI Design
4.0
5.0
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
EE415 VLSI Design
In2
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
EE415 VLSI Design
Delay in Transmission Gate Networks
5
5
V1
In
5
Vi
Vi-1
C
0
5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
EE415 VLSI Design
CC
C
C
(c)
CC
Vn
C
Elmore Delay (Chapter 8)
Vin
R1
R2
1
C1
C2
2
Ri-1
Ci-1
i-1
Ri
i
Ci
RN
N
CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin, then delay at node N is
t
N
N
N
N
i
=  R  C =  C  R
i
j
i
j
i =1 j =i
i =1 j =1
See page 475
EE415 VLSI Design
Delay Optimization
EE415 VLSI Design
NMOS Only Logic: Level Restoring Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
EE415 VLSI Design
Level Restoring Transistor
5.0
with
5.0
Vout (V)
without
3.0
VX
VB
1.0
-1.00
without
3.0
with
2
t (nsec)
1.0
4
(a) Output node
EE415 VLSI Design
6 -1.00
2
4
t (nsec)
(b) Intermediate node X
6
Solution 3: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V
5V
VDD
0V
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS
EE415 VLSI Design
Complimentary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
EE415 VLSI Design
A
F=AÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
EXOR/NEXOR
F=AÝ
4 Input NAND in CPL
EE415 VLSI Design
Standard Cell Layout
Methodology
Appendix C
Page 264
EE415 VLSI Design
Standard Cell Layout Methodology
metal1
VDD
Well
VSS
Routing Channel
signals
EE415 VLSI Design
polysilicon
Two Versions of (a+b).c
VDD
VDD
x
x
GND
a
c
b
(a) Input order {a c b}
EE415 VLSI Design
GND
a
b
c
(b) Input order {a b c}
Logic Graph
VDD
x
b
j
c
c
a
PUN
i
x
VDD
x
b
c
j
a
PDN
i
GND
a
b
Euler Path
EE415 VLSI Design
Consistent Euler Path
x
c
i
x
b
a
j
GND
{ a b c}
EE415 VLSI Design
VDD
Example: x = ab+cd
x
x
c
b
VDD
x
a
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
EE415 VLSI Design
c
b
Combinational Logic:
Dynamic CMOS
Read Section 4.3
EE415 VLSI Design
Dynamic Logic
VDD
f
VDD
f
Mp
Me
Out
CL
In1
In2
In3
PDN
In1
In2
In3
PUN
Out
f
Me
f
fn network
2 phase operation:
EE415 VLSI Design
Mp
fp network
• Precharge
• Evaluation
CL
Example
VDD
f
Mp
• N + 1 Transistors
Out
• Ratioless
• No Static Power Consumption
• Noise Margins small (NML)
A
C
B
f
Me
EE415 VLSI Design
• Requires Clock
Transient Response
6.0
f
Vout (Volt)
4.0
Vout
EVALUATION
PRECHARGE
2.0
0.0
0.00e+00
EE415 VLSI Design
2.00e-09
t (nsec)
4.00e-09
6.00e-09
Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
f
EE415 VLSI Design
GND