Download EE4800 CMOS Digital IC Design & Analysis

EE4800 CMOS Digital IC Design & Analysis
Lecture 2 CMOS Circuits and Layout
Zhuo Feng
2.1
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Complementary CMOS
■ Complementary CMOS logic gates
► NMOS pull-down network
pMOS
pull-up
network
► PMOS pull-up network
inputs
output
2.2
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float)
1
Pull-down ON
0
X (shorted)
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
nMOS
pull-down
network
Series and Parallel
■
■
■
■
NMOS: 1 = ON
PMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
a
a
g1
g2
1
1
0
1
0
1
b
b
b
OFF
OFF
OFF
ON
a
a
a
a
0
0
1
1
0
1
0
1
b
(b)
a
g2
(c)
a
g1
g2
b
(d)
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
2.3
b
a
g1
a
0
(a)
g2
a
0
b
g1
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
Conduction Complement
■
■
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
► Series nMOS: Y=0 when both inputs are 1
► Thus Y=1 when either input is 0
► Requires parallel pMOS
Y
A
■
Rule of Conduction Complements
► Pull-up network is complement of pull-down
► Parallel -> series, series -> parallel
2.4
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
B
Compound Gates
■ Compound gates can do any inverting function
■ Example: Y  A  B  C  D (AND-AND-OR-INVERT, AOI22)
A
C
A
C
B
D
B
D
(b)
(a)
A
D
B C
(c)
D
A
B
(d)
C
D
A
B
A
B
C
D
Y
A
C
B
D
(f)
(e)
2.5
C
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Y
Example: O3AI
Y   A B C D
A
B
C
D
Y
D
A
2.6
B
C
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Signal Strength
■ Strength of signal
► How close it approximates ideal voltage source
■ VDD and GND rails are strongest 1 and 0
■ NMOS pass strong 0
► But degraded or weak 1(the high voltage is less than VDD)
■ PMOS pass strong 1
► But degraded or weak 0
■ Thus nMOS are best for pull-down network
2.7
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Pass Transistors
■ Transistors can be used as switches
► Pass transistor: NMOS or PMOS is used alone as an imperfect
switch
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
d
g=0
g
s
s
g=1
1
Input
d
d
g=1
s
2.8
d
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Transmission Gates
■ Pass transistors produce degraded outputs
■ Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
b
gb
2.9
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
a
g
b
gb
Output
a
b
gb
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Tristates
■ Tristate buffer produces Z when not enabled
EN
EN
0
0
1
1
A
0
1
0
1
Y
Z
Z
0
1
Y
A
EN
Y
A
EN
2.10
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Nonrestoring Tristate
■ Transmission gate acts as tristate buffer
► Only two transistors
► But nonrestoring
▼ Noise on A is passed on to Y
▼ After several stages of nonrestoring logic, a signal can be too
degraded to recognize
▼ Delay of a series of such nonrestoring gates increases
quadratically with the number of gates in series
EN
A
Y
EN
2.11
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Tristate Inverter
■ Tristate inverter produces restored output
► Violates conduction complement rule (when EN=0)
► Distributing enable signals in a timely fashion across a
entire chip is very difficult
► Multiplexers are preferred
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
2.12
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Multiplexers
■ Key components in CMOS memory elements
and data manipulation structures
■ 2:1 multiplexer chooses between two inputs
2.13
S
D1
D0
Y
0
0
1
1
X
X
0
1
0
1
X
X
0
1
0
1
S
D0
0
Y
D1
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
1
Gate-Level Mux Design
■ Y  SD1  SD0 (too many transistors)
■ How many transistors are needed? 20
D1
S
D0
D1
S
D0
2.14
Y
4
2
4
2
4
2
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
2
Y
Transmission Gate Mux
■ Nonrestoring mux uses two transmission gates
► Only 4 transistors
S
D0
Y
S
D1
S
2.15
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Inverting Mux
■ Inverting multiplexer
► Use compound AOI22
► Or pair of tristate inverters
► Essentially the same thing
■ Noninverting multiplexer adds an inverter
D0
S
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
Y
S
D1
2.16
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
0
1
4:1 Multiplexer
■ 4:1 mux chooses one of 4 inputs using two
selects
► Two levels of 2:1 muxes
► Or four tristates
S1S0 S1S0 S1S0 S1S0
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
2.17
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D Latch
■ When CLK = 1, latch is transparent
► D flows through to Q like a buffer
■ When CLK = 0, the latch is opaque
► Q holds its old value independent of D
■ a.k.a. transparent latch or level-sensitive latch
D
2.18
Latch
CLK
CLK
D
Q
Q
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D Latch Design
■ Multiplexer chooses D or old Q
CLK
D
1
CLK
Q
Q
Q
D
Q
0
CLK
CLK
CLK
2.19
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D Latch Operation
Q
D
Q
CLK = 1
Q
D
CLK = 0
CLK
D
Q
2.20
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Q
D Flip-flop
■
■
■
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave flip-
flop
■
Collection of two or more D flip-flops sharing a common
clock input is called a register (multi-bit)
CLK
D
Flop
CLK
D
Q
Q
2.21
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
D Flip-flop Design
■ Built from master and slave D latches
CLK
CLK
CLK
QM
D
D
CLK
QM
Latch
Latch
CLK
CLK
CLK
CLK
Q
CLK
2.22
Q
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
CLK
D Flip-flop Operation
D
QM
Q
CLK = 0
D
QM
CLK = 1
CLK
D
Q
2.23
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Q
Race Condition
■ Back-to-back flops can malfunction from clock skew
► Second flip-flop fires late
► Sees first flip-flop change and captures its result
► Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
D
Flop
CLK1
CLK2
Q2
Q1
Q2
2.24
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Nonoverlapping Clocks
■ Nonoverlapping clocks can prevent races
► As long as nonoverlap exceeds clock skew
► Industry manages skew more carefully
2
1
QM
D
2
2
2
Q
1
1
1
1
2
2.25
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Layout
■ Chips are specified with set of masks
■ Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
■ Feature size f = distance between source and
drain
► Set by minimum width of polysilicon
■ Feature size improves 30% every 3 years or so
■ Normalize for feature size when describing
design rules
■ Express rules in terms of l = f/2
► E.g. l = 0.3 mm in 0.6 mm process
2.26
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Simplified Design Rules
■ Conservative rules to get you started
2.27
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Inverter Layout
■ Transistor dimensions specified as Width / Length
► Minimum size is 4l / 2l, sometimes called 1 unit
► In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
2.28
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Gate Layout
■ Layout can be very time consuming
► Design gates to fit together nicely
► Build a library of standard cells
■ Standard cell design methodology
► VDD and GND should abut (standard height)
► Adjacent gates should satisfy design rules
► nMOS at bottom and pMOS at top
► All gates include well and substrate contacts
2.29
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Example: Inverter
2.30
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Example: NAND3
■ Horizontal N-diffusion and P-diffusion strips
■ Vertical polysilicon gates
■ Metal1 VDD rail at top
■ Metal1 GND rail at bottom
■ 32 l by 40 l
2.31
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Stick Diagrams
■ Stick diagrams help plan layout quickly
► Need not be to scale
► Draw with color pencils or dry-erase markers
VDD
VDD
A
A
B
C
c
Y
GND
2.32
INV
Y
GND
NAND3
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
metal1
poly
ndiff
pdiff
contact
Wiring Tracks
■ A wiring track is the space required for a wire
► 4 l width, 4 l spacing from neighbor = 8 l pitch
■ Transistors also consume one wiring track
2.33
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Well spacing
■ Wells must surround transistors by 6 l
► Implies 12 l between opposite transistor flavors
► Leaves room for one wire track
2.34
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Area Estimation
■ Estimate area by counting wiring tracks
► Multiply by 8 to express in l
40 l
32 l
2.35
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Example: O3AI
■ Sketch a stick diagram for O3AI and estimate area
►
Y  A B C D
VDD
A
B
C
D
Y
GND
5 tracks =
40 l
2.36
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
6 tracks =
48 l