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AIDA: LEC-HEC connection
Davide Braga
Steve Thomas
ASIC Design Group
16September 2010
New link between low and high channels:
In this technology forward-biased
diodes suffer of parasitic bipolar
structure to the substrate.
-increased the size of clamp transistor
to reduce resistance (~100s Ohm)
-diodes have been replaced with diodeconnected transistors: they are effective
but slower (for the charge to flow they
need to wait for the creation of the
channel) and susceptible to threshold
variation
2
Parametrized input current:
Only one parameter d to model the input charge:
for a given area (charge Q) d is swept to simulate increased
collection time from the detector.
NB: this does not account for plasma effect in the detector so
expect pessimistic simulations for high energy implants!
NB2: input capacitance Cin=10pF
Q/2d
ed=1
d=2
h+
Q/6d
d
d=3
3d
3
High ref, Qin=900pC (~18GeV) (1):
HEC preamp out (d=100ns)
-with input diode-connected
transistors
-without (charge loss)
Vin (d=100ns)
-with input diode-connected
transistors
-without
Input Current:
charge (area) and shape
constant but different
collection times from detector
Vin (d=200ns)
no significant difference
between the two, the diodeconnected transistors don’t
conduce
Vin (d=300ns)
4
High ref, Qin=900pC (~18GeV) (2):
Vin
Input current
(d=100ns-200ns-300ns)
HEC preamp output
Charge flowing through
clamp transistor
Charge flowing through diode
connected transistors
5
High ref, Qin=900pC (~18GeV) (3):
Charge flowing through
clamp transistor
(d=100ns-200ns-300ns)
Charge flowing through
diode-connected
transistors
HEC preamp output for
different d
Sampled value once the
output has settled
For the fastest collection
time (d=100ns) we lose
~5% of the input charge
6
High ref, Qin=900pC (~18GeV) (4):
Current in the diodeconnected transistor
equivalent resistance
equivalent resistance
(detail)
7
High ref, Qin=500pC (~10GeV) (1):
Vin
OK if
d~>100ns
Input current
(d=50ns-100ns-150ns)
Comparator switching in
HEC preamp output
8
High ref, Qin=500pC (~10GeV) (2):
HEC preamp output
Vin (d=50ns-100ns-150ns)
for d=50ns we lose 5.7%
of input charge.
NB: no ballistic deficit considered
Charge transferred to the
HEC (loss for d=50ns)
HEC preamp output
(detail):
no charge loss for
d~>100ns
Charge lost in a forwardbiased pmos in the LEC
9
High ref, Qin=100pC (~2GeV):
Vin
Input current
(d=20ns-40ns-60ns)
Within
power
supplies
10
High ref, Qin=50pC (~1GeV):
Vin
Input current
(d=10ns-30ns-50ns)
Within
power
supplies
11
Low ref, Qin=900pC (~18GeV) (1):
Vin
Input current
(d=100ns-200ns-300ns)
Input voltage shouldn’t
reverse-bias the substrate
even in worst case (d=100ns)
Comparator switching in
HEC preamp output
12
Low ref, Qin=900pC (~18GeV) (2):
Current in the diodeconnected transistor
equivalent resistance
equivalent resistance
(detail)
13
Low ref, Qin=500pC (~10GeV):
Vin
Input current
(d=50ns-100ns-150ns)
Input voltage shouldn’t
reverse-bias the substrate
if d~>100ns
Comparator switching in
HEC preamp output
14
Low ref, Qin=100pC (~2GeV):
Vin
Input current
(d=20ns-40ns-60ns)
Input voltage shouldn’t
reverse-bias the substrate
if d~>40ns
Comparator switching in
HEC preamp output
15
Low ref, Qin=50pC (~1GeV):
Vin
Input current
(d=10ns-30ns-50ns)
Input voltage shouldn’t
reverse-bias the substrate
if d~>30ns
Comparator switching in
HEC preamp output
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