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Progettazione di circuiti e sistemi VLSI
Anno Accademico 2010-2011
Lezione 5
15/18.3.2011
L’inverter CMOS
L'Inverter CMOS
1
The CMOS Inverter: A First
Glance
V DD
V in
V out
CL
L'Inverter CMOS
2
CMOS Inverter
N Well
VDD
VDD
PMOS
2l
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
L'Inverter CMOS
3
Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal
L'Inverter CMOS
4
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Rn
V in = V DD
V in = 0
L'Inverter CMOS
5
CMOS Inverter: Transient
Response
V DD
V DD
tpHL = f(R n .CL)
= 0.69 Rn CL
Rp
V out
V out
CL
CL
Rn
V in = 0
V in = V DD
(a) Low-to-high
(b) High-to-low
L'Inverter CMOS
6
Voltage Transfer
Characteristic
L'Inverter CMOS
7
PMOS Load Lines
VDD
PMOS
IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
In
Out
NMOS
V out
IDp
IDn
IDn
Vin=0
Vin=0
Vin=1.5
Vin=1.5
V DSp
V DSp
Vout
VGSp=-1
VGSp=-2.5
Vin = V DD+VGSp
IDn = - IDp
L'Inverter CMOS
Vout = V DD+VDSp
8
CMOS Inverter Load Characteristics
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
NMOS
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 1
Vin = 2
Vin = 0.5
Vin = 2.5
Vin = 0
Vout
L'Inverter CMOS
9
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1L'Inverter
1.5
CMOS 2
NMOS res
PMOS off
2.5
Vin
10
Switching Threshold as a
function of Transistor Ratio
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
1.2
1.1
1
0.9
0.8
10
0
10
L'Inverter CMOS
W /W
p
n
1
11
Determining VIH and VIL
Vout
V OH
VM
V in
V OL
V IL
V IH
A simplified approach
L'Inverter CMOS
12
Inverter Gain
0
-2
-4
gain
-6
-8
-10
-12
-14
-16
-18
0
0.5
1
1.5
2
2.5
V (V)
in
L'Inverter CMOS
13
Simulated VTC
2.5
l
VIL=1.03
VIH=1.45
2
NMH=1.05
1.5
Vout(V)
NML=1.03
1
0.5
0
0
0.5
1
1.5
2
2.5
V (V)
in
L'Inverter CMOS
14
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
2
2.5
0
0
V (V)
0.05
0.1
V (V)
0.15
0.2
in
in
L'Inverter CMOS
15
Impact of Process
Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
L'Inverter CMOS
16
Propagation Delay
L'Inverter CMOS
17
CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
CL
kn VDD
Vin = V DD
L'Inverter CMOS
18
CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
L'Inverter CMOS
t
19
CMOS Inverters
VDD
PMOS
1.2mm
=2l
Out
In
Metal1
Polysilicon
NMOS
GND
L'Inverter CMOS
20
Transient Response
3
2.5
?
Vout(V)
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
1
tpHL
tpLH
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
-10
x 10
L'Inverter CMOS
21
Design for Performance
• Keep capacitances small
• Increase transistor sizes
– watch out for self-loading!
• Increase VDD (????)
L'Inverter CMOS
22
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
L'Inverter CMOS
23
NMOS/PMOS ratio
-11
5
x 10
tpHL
tpLH
tp(sec)
4.5
b = Wp/Wn
tp
4
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
b
L'Inverter CMOS
24
Inverter Sizing
Due inverter in cascata  CL=(Cdp1+Cdn1)+ (Cgp2+Cgn2)
+ CW= (1+β)(Cdn1+Cgn2) +Cw 
tp=(tpHL +tpLH)/2=0.69 CL(Reqn+Reqp)/2 =
=0.345 ((1+β)(Cdn1+Cgn2) +CW) Reqn(1+r/β)
dove r=Reqp/Reqn con stesse dimensioni PMOS e
NMOS
per δtp/δβ= 0 βopt=sqrt (r (1+ CW/(Cdn1+Cgn2)))
L'Inverter CMOS
25
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
L'Inverter CMOS
26
Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 WP 

RP  Runit 
 Wunit 
-1
 WN 

Runit 
 Wunit 
tpHL = (ln 2) RNCL
-1
2W
W
 RN  RW
tpLH = (ln 2) RPCL
Delay (D):
W
Cunit
Load for the next stage: C gin  3
Wunit
L'Inverter CMOS
27
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
L'Inverter CMOS
28
Inverter with Load
CP = 2Cunit
Delay
2W
W
Cint
CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
L'Inverter CMOS
29
Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint = Cgin with   1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
L'Inverter CMOS
30
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin, j 1 

t pj ~ RunitCunit 1 
 C

gin
,
j


N
N 
C gin, j 1 
, C gin, N 1  C L
t p   t p , j  t p 0  1 
 C

j 1
i 1 
gin, j 
L'Inverter CMOS
31
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j  C gin, j -1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
L'Inverter CMOS
32
Optimum Delay and Number
of Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F / 
L'Inverter CMOS

33
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
L'Inverter CMOS
34
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
CL  F  Cin  f Cin with N 
ln f
t p 0 ln F  f


t p  Nt p 0 F /   1 

  ln f ln f
t p t p 0 ln F ln f - 1 -  f


0
2
f

ln f
1/ N
For  = 0, f = e, N = lnF
L'Inverter CMOS



f  exp 1   f 
35
Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp 1   f 
fopt = 3.6
for =1
L'Inverter CMOS
36
Normalized delay function of F

t p  Nt p 0 1  N F / 
L'Inverter CMOS

37
Power Dissipation
L'Inverter CMOS
38
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
L'Inverter CMOS
39
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
L
Energy/transition = C * V
2
dd
2
dd
Power = Energy/transition *f*
Not a function of Ltransistor
sizes!
dd
Need to reduce C , V , and f to reduce power.
L'Inverter CMOS
40
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E0
1
= CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
L'Inverter CMOS
41
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N 
P avg = lim --------  fclk =  lim ----------- C  Vdd  f clk
N   N 
N N
L
0  1 =
n N 
lim -----------N N
P avg = 0 1  C  Vdd 2  f clk

L
L'Inverter CMOS
42
Energy Delay Product
PDP (Power Delay Product) =
PavTp=CLVDD2/2 Energia per
commutazione
EDP = PDP x tp tp=αCLVDD/(VDD-VTe) dove
VTe=VT+VDSAT/2
EDP = αCL2VDD3/2(VDD-VTe)
VDDopt = 3/2VTe
L'Inverter CMOS
43