Download Detector options

http://www.linearcollider.org
http://www.fnal.gov/directorate/icfa/LC_parameters.pdf
October 5th 2005
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and Radiation Hardness of Semiconductor Detectors
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The ILC Silicon Vertex
(talk summary)
3.
1.
ILC introduction
•
•
•
•
2.
Physics goals
Main accelerator characteristics
Detector options
Vertex constrains
3.
4.
4.
CCD
DEPFET
MAPS
SOI
5.
October 5th 2005
SUCIMA
PRIN
MIMOSA
Projects description
3.
4.
6.
Brief history
Groups involved
Previous Italian projects
3.
4.
5.
Vertex detector technologies
•
•
•
•
Italian proposal for the ILC
goals
activities
Conclusion
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Cross
sections
Benchmark
reactions
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ILC Working plan (LCWS 05, Snowmass 05)
by Barry Barish GDE (Global Disegn Effort) Director
2004
2005
2006
2007
2008
GDE (Design)
2009
2010
(Construction)
Technology
Choice
Acc.
CDR
TDR
Start Global Lab.
Done!
Det.
Detector Outline
Documents
CDRs
LOIs
Detector R&D Panel
Detector
R&D Phase
Collaboration
Forming
Construction
Tevatron
SLAC B
HERA
October 5th 2005
LHC
T2K
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http://www.fnal.gov/directorate/icfa/LC_parameters.pdf
• s = 200 – 500 GeV  1 TeV
• Luminosity = 2 x 10**34 cm-2 s-1
• Integrated Luminosity 500 fb-1 (first four years)
• 2 interaction regions with easy switching
( one @ 20mrad crossing angle)
• No. Bunch/train
2820
• Interbunch time
 300 ns
• Intertrain time
 200 ms
• beam dimensions:
 x = 543 nm
 y = 5.7 nm
 z = 300  m
• Beam power
11 MW
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Detector concepts
US
B field:
Sid:
5T
LDC: 4T
GLD: 3T
October 5th 2005
EU
ASIA
Design based on
charged and neutral shower
separation
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Vertex main parameters
Main task
heavy flavor tagging
Geometry and
impact parameter
resolution
Rin = 15 mm
Rout = 60 mm
ip = [5  10/p sin 3/2 ] m
Intrinsic resolution
and
maximum thickness
• point ~ 2.5m
• thickness ~ 0.1%X0/layer
(~100 m)
• background level -> 20 s readout time
• radiation hardness
( ~ 109 n/cm2/anno e 5*1012 e/cm2/year)
• cooling, support structure
• EMI compliant
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Vertex detector technologies under study
Detector
teckhnology
Parallel Column
readout
In situ storage
Sparse data
scan
CCD
LCFI (UK)
LCFI-ISIS
-
CMOS
IRES (Strasbourg)
RAL-FAPS
Difficult
SOI
SUCIMA
(Uninsubria et al)
Possible
Possible
DEPFET
MPI-Bonn et al (D)
-
-
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Frascati
Brainstorming meeting
(June 7-8 2005)
P-ILC project submitted
to INFN Gr. I scientific
committee
(approved September 2005)
Groups involved in the project
1. Insubria (M. Caccia - SUCIMA FP5):
•
Monolithic sensors on high
resistivity substrate (tecnology
•
SOI – NDA with HAMAMATSU)
backthinnig to 15 micron
•
large area sensors (~ cm2) high
radiation tolerant (~ 2 Mrad)
2. ROMA III (E. Spiriti – INFN Gr5):
•
Prototype TSMC 0.25 micron under
test
3. Bergamo (Valerio Re – PRIN):
•
Prototype ST 0.13 micron
available
4. Ferrara (L. Piemontese)
•
Readout board under development
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P-ILC project program
• Implementation of a SDS (Sparse Data Scan) system on Pixel
• design and construction of a data acquisition system for a 1 Mpixel sensor
• design and construction of a reference telescope to characterize
sensors under development on beam
• goal:
architecture compatible with a background rate of ~ 5
hit/cm2/bunch crossing  frame rate of 50 kHz (20 s), and with a single
point resolution and a minimization of multiple scattering able to maintain
an impact parameter resolution of 5  10/(P sin 3/2 ) m
• main problem: implementation of PMOS transistor on pixel without loosing
charge collection efficiency
• “workhorse”: 0.13 m tecnology with “triple well”;
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Miminum Ionising particle MOS Active pixel sensors
Reset transistor
Source follower
Row selection
Monolithic Active Pixel Sensors
(MAPS)
for visible light
applied to high position resolution
ionizing particle detection
Collecting diode
• Based on charge generation/collection in
the epitaxial layer (thickness 2-14 m,
tecnology dependent) (signal: ~80 pair eh/ m)
• Charge collection by diffusion
(undepleted sensitive volume 
cluster charge radius ~ 50 m
collection time ~ 150 ns)
• Simple 3 transistor architecture
• Based on standard microelectronics
processes easily accessible on the market
(e.g. ~ 50 kEUR per engineering run,
tecnology AMS 0.6 m, 3 wafers + 3)
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Triple-well CMOS processes
In triple-well CMOS processes
a deep nwell is used to
provide N-channel MOSFETs
with better insulation from
digital signals
This feature can be
exploited in the design of
CMOS pixels:
the deep n-well can be used as the collecting electrode
N-channel transistors can be laid out in the collecting electrode area
NMOSFETs built in the deep n-well are shielded against digital noise
Use of the deep n-well was proposed by Turchetta et al. (2004 IEEE NSS Conference Record, N28-1) to
address radiation hardness issues
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Deep n-well sensor
Standard readout
channel for capacitive
detectors is used for
Q-V conversion
Charge sensitivity is
independent of the sensor
capacitance
NMOS devices of the analog section built in the deep n-well
PMOS devices needed for full exploitation of CMOS
technology functionalities
Ratio of the deep n-well area to the area covered by all the
n-type wells should be kept as large as possible (never less
than 0.8 in the prototype test structures)
Readout scheme compatible with existent
architectures for data sparsification at the level of
the elementary cell
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A novel kind of CMOS MAPS has been designed and fabricated in a
0.13 m CMOS technology
Deep n-well is used as the sensitive electrode; a standard readout
channel for capacitive detectors is employed to amplify the charge
signal
Tests with a laser source demonstrated that the sensor is capable of
collecting and processing the charge
Tests with radioactive sources are in progress
Plans for the future:
Optimization of the readout electronics and of the sensitive electrode
layout (capacitance minimization)
Design of a matrix with self trigger capability and sequential readout
Submission of the same design in a different CMOS process (IBM,
non epitaxial, triple well, 0.13 m process, available through MOSIS,
and/or CMOS process with optoelectronic features)
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SUCIMA objectives
Requirements for
end-user applications:
• Sensitive area
TERA  70x70 mm2
BRACHY  70x30 mm2
• Granularity (pixel pitch)
TERA  1 mm
BRACHY  0.1mm
• Readout speed
TERA 104 frame/s
BRACHY no spec. Requir.
• Dynamic range
TERA 104  108 el/mm2/s
BRACHY 150 mip/100s
• Radiation tolerance
TERA 55000 rad/s
BRACHY 222 rad/s
October 5th 2005
Development of an advanced imaging technique
of extended radioactive sources used in
medical applications
(“imaging” intended as the record of a dose map)
End-user applications:
• Intravascular Brachytherapy
• Real-time monitor of a proton beam
for radiotherapic treatments
Detector options:
• CMOS imagers, well established industrial fabrication
process that guarantees the access to most advanced
technologies
• SOI imagers, new technology integrating Silicon
detector with readout electronics on the same wafer
• Hybrid Strip/pad Detectors, engineering development
based on commercial available front-end chips and
sensors, providing a reduced set of information but
easily implemented
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SUCIMA
SOI (Silicon On Insulator)
Meeting con mr. YAMAMOTO, HAMAMATSU PHOTONICS
Possible collaboration on high granularity tracking detector development with
SOI technology (September 6th; + Bonn, AGH-Krakow, KEK(?))
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MAPS (Monolithic Active Pixel Sensors)
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State of the art SUCIMA-in-itinere
Sensitivity to
low energy
electrons
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•
major development:
a. increase the radiation tolerance to ionizing radiation
55Fe,
5.9 keV line
• before the irradiation
• after 200 krad
• after 400 krad
500
400
0krad
500krad
1000krad
300
200
State of the art ante-SUCIMA
100
100
200
300
400
State of the art SUCIMA-in-itinere
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MIMOSA ISE/TCAD
simulation
Substrato
n+ ~1020 cm-3
~1019 cm-3
pwell ~1017 cm-3
Epitaxial ~1015 cm-3
1200
1000
Pixel 5
Pixel 2
Pixel 1
Pitch = 20 m
Nwell diode 3x3 m
~90000 vertex
Carica [e]
800
Collection
time
~100 ns
600
400
200
0
0
5 10
-8
1 10
-7
1,5 10
-7
2 10
-7
2,5 10
-7
3 10
-7
3,5 10
-7
4 10
-7
Tempo [s]
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MIMOSA chip (designed at Roma3)
Pitch = 17m
4096 pixels
Pitch = 34m
1024 pixels
Test
structures
• TSMC 0.25 m
• 8 m epi thickness
• gate all around design
for radiation hardness
• different pixels architecture
( different collecting diode
number and dimensions)
Chip
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MIMOSA chip
(designed at Roma3)
first results
Alfa event
large pitch (34 m)
Alfa event
small pitch (17 m)
October 5th 2005
X
sources
@
5.9 KeV
8.4 Kev
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Preparing a reference
microstrip tracker
for pixel detector test
on particles beam
12 layer of microstrip detectors
(6x+6y)
Readout pitch of 44 m pitch
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Conclusions
• Two technologies, at least, could meet the requirements for
SDS ( Sparse Data Scan ) implementation
• The R&D time scale needed for such implementation
seems to meet the overall ILC project time scale
• Italian groups, including possible new comers, have sufficient
background and know-how in the field to contribute significantly
to the overall project
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