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ECE2030
Introduction to Computer Engineering
Lecture 4: CMOS Network
Prof. Hsien-Hsin Sean Lee
School of ECE
Georgia Institute of Technology
1
CMOS Inverter

Connect the following terminals of a PMOS and an NMOS


Gates
Drains
Vdd
Vdd
Vin
PMOS
Vout
NMOS
Ground
2
Vin
Vdd
OFF
Vin
Vout
Vin
ON
Gnd
Vin = HIGH
Vout = LOW (Gnd)
ON
Vout
Vin
OFF
Gnd
Vin = LOW
Vout = HIGH (Vdd)
H.-H. S. Lee
CMOS Voltage Transfer Characteristics
Vdd
Vin
PMOS
Vout
NMOS
Gnd
OFF: V_GateToSource < V_Threshold
LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold
SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource
Note that in the CMOS Inverter  V_GateToSource = V_in
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H.-H. S. Lee
Pull-Up and Pull-Down Network




CMOS network consists of a PullUP Network (PUN) and a PullDown Network (PDN)
PUN consists of a set of PMOS
transistors
PDN consists of a set of NMOS
transistors
PUN and PDN implementations
are complimentary to each other


4
Vdd
PUN
OUPTUT
….
I0
I1
PMOS  NOMS
In-1
Series topology Parallel topology
PDN
Gnd
H.-H. S. Lee
PUN/PDN of a CMOS Inverter
Vdd
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
5
A
B
0
1
1
Z
A
B
0
Z
1
0
A
B
0
1
1
0
B
A
Gnd
CMOS Inverter
H.-H. S. Lee
Gate Symbol of a CMOS Inverter
Vdd
A
B
B
A
B=Ā
Gnd
CMOS Inverter
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H.-H. S. Lee
PUN/PDN of a NAND Gate
Pull-Up
Network
Pull-Down
Network
A
B
C
0
0
1
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
Z
0
1
Z
1
0
Z
1
1
0
Vdd
B
A
C
A
B
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H.-H. S. Lee
PUN/PDN of a NAND Gate
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
8
A
B
C
0
0
1
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
Z
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
1
0
1
1
1
0
1
1
1
0
Vdd
B
A
C
A
B
H.-H. S. Lee
NAND Gate Symbol
Truth Table
A
B
C
0
0
1
0
1
1
1
0
1
1
1
0
Vdd
B
A
C
A
A
C
B
B
C  AB
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H.-H. S. Lee
PUN/PDN of a NOR Gate
Pull-Up
Network
Pull-Down
Network
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A
B
C
0
0
1
0
1
Z
1
0
Z
1
1
Z
A
B
C
0
0
Z
0
1
0
1
0
0
1
1
0
Vdd
A
B
C
A
B
H.-H. S. Lee
PUN/PDN of a NOR Gate
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
11
A
B
C
0
0
1
0
1
Z
1
0
Z
1
1
Z
A
B
C
0
0
Z
0
1
0
1
0
0
1
1
0
A
B
C
0
0
1
0
1
0
1
0
0
1
1
0
Vdd
A
B
C
A
B
H.-H. S. Lee
NOR Gate Symbol
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
0
A
B
C
A
C
A
B
B
C AB
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H.-H. S. Lee
How about an AND gate
Vdd
B
A
Vdd
C
A
C
B
A
C=AB
B
Gnd
Inverter
NAND
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H.-H. S. Lee
An OR Gate
Vdd
A
Vdd
B
C
A
C
B
B
A
C  AB
Gnd
Inverter
NOR
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H.-H. S. Lee
What’s the Function of the following
CMOS Network?
Vdd
A
B
Pull-Up
Network
A
B
C
A
B
A
B
Pull-Down
Network
Combined
CMOS
Network
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A
B
C
0
0
Z
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
0
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
Function = XOR
H.-H. S. Lee
Yet Another XOR CMOS Network
Vdd
A
B
Pull-Up
Network
A
B
C
A
B
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Pull-Down
Network
A
B
Combined
CMOS
Network
A
B
C
0
0
Z
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
0
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
Function = XOR
H.-H. S. Lee
Exclusive-OR (XOR) Gate
Vdd
Truth Table
A
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
A
A
B
B
C
C
A
A
B
B
B
C  AB AB  A  B
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H.-H. S. Lee
How about XNOR Gate
Truth Table
A
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
How do we draw the
corresponding CMOS network
given a Boolean equation?
C
B
C  AB AB  A  B
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H.-H. S. Lee
How about XNOR Gate
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
A
A
A
Vdd
B
B
C
A
A
C
B
B
B
Inverter
C  AB AB
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XOR
H.-H. S. Lee
A Systematic Approach


Each variable in the given Boolean eqn corresponds
to a PMOS transistor in PUN and an NMOS
transistor in PDN
Draw PUN using PMOS based on the Boolean eqn




Invert each variable of the Boolean eqn as the gate
input for each PMOS in the PUN
Draw PDN using NMOS in complementary form




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AND operation drawn in series
OR operation drawn in parallel
Parallel (PUN) to series (PDN)
Series (PUN) to parallel (PDN)
Label with the same inputs of PUN
Label the output
H.-H. S. Lee
Example 1
In parallel
Vdd
F  AC  B
In series
(1) Draw the Pull-Up Network
21
H.-H. S. Lee
Example 1
Vdd
In parallel
F  AC  B
In series
A
B
C
(2) Assign the complemented input
22
H.-H. S. Lee
Example 1
Vdd
In parallel
F  AC  B
In series
(3) Draw the Pull-Down Network in
the complementary form
23
A
B
C
A
C
H.-H. S. Lee
Example 1
Vdd
In parallel
F  AC  B
In series
(3) Draw the Pull-Down Network in
the complementary form
A
B
C
C
A
B
24
H.-H. S. Lee
Example 1
Vdd
In parallel
F  AC  B
In series
A
B
C
F
Label the output F
C
A
B
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H.-H. S. Lee
Example 1
Vdd
In parallel
A
F  AC  B
B
C
In series
Truth Table
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A
B
C
F
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
F
C
A
B
H.-H. S. Lee
An Alternative for XNOR Gate
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
A
A
A
B
B
C
C
A
B
B
C  AB AB
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A
B
H.-H. S. Lee
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
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D
H.-H. S. Lee
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
D
A
C
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H.-H. S. Lee
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
A
D
B
C
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H.-H. S. Lee
Example 3
Vdd
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
Pull-Up
Network
D
B
F
A
A
D
B
Pull-Down
Network
C
31
H.-H. S. Lee
Example 4
Vdd
F  (E  D)  (A  D  B  (A  C))
E
D
Start from the innermost term
A
C
B
Pull-Up
Network
A
D
F
A
A
D
E
Pull-Down
Network
B
D
C
32
H.-H. S. Lee
Another Example
F  AC  B
33
How ??
H.-H. S. Lee