Download A Fully-Automated Process Characterization Macro for

Introduction to Time Dependent
Dielectric Breakdown in Digital Circuits
Trap
0V
n+
VCC
Conduction
Path
0V
n+
Stressed NMOS Cross Section
Breakdown
IGATE paths
Breakdown in Digital Circuits
• Traps generated under the
influence of electric field
• Gate dielectric no longer a
reliable insulator
• Statistical process
requires large # of tests
for characterization
Time-to-Breakdown CDFs
1
An Array-Based Test Circuit for Fully
Automated TDDB Characterization
Stress Cell Abstraction
Wafer Probe Station
Select
Stressed
Device
A/D Current
Monitor
IG
SCANOUT
Save:
(1) Time
(2) $$$$
32x32 Array
of Stress
Cells
+
Selection
Logic
Bitline
VSTRESS
Proposed System
• Measure 32x32 array of stressed transistors in parallel
without a probe station
• 16b results scanned out and stored for post-processing
• Efficient collection of failure statistics by running a
simple control program
2
Measured TBD Results
ln(-ln(1-F))
ln(-ln(1-CDF))
2
2
1
1
30oC
(1)
(2)
(3)
(4)
0
0
-1
-1
-2
-2
-3
-3
-4
-4
-5
-5
-2
-1
3.8V through
4.3V stress
01
23
45 67 89 10
11 12
13
TFAIL(ln(a.u.))
(ln(s))
TBDTor
TFAIL
BD or
Fast Statistical Characterization
Analysis of Spatial Correlation
• Array-based design  define a
CDF with a single test and
check spatial correlation
• Parallel stressing  large
experiment speedup
• Cheap & accessible test setup
Measurement Lab Setup
3